drm/vc4: Extend the validator for VS/CS.

We need the GL shader packets to light up the VS/coord shader pair.

Signed-off-by: Eric Anholt <eric@anholt.net>

4 files changed, 314 insertions, 55 deletions

diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 2d449ad2bb80..a2eff695de68 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -112,7 +112,11 @@ struct exec_info {
 	 * it's expected to be found at.  It gets read in from the
 	 * command lists.
 	 */
-	uint32_t *shader_state;
+	struct vc4_shader_state {
+		uint8_t packet;
+		uint32_t addr;
+	} *shader_state;
+
 	/** How many shader states the user declared they were using. */
 	uint32_t shader_state_size;
 	/** How many shader state records the validator has seen. */
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 81eeb401d519..b1409a830f6e 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -246,12 +246,13 @@ vc4_cl_validate(struct drm_device *dev, struct drm_vc4_submit_cl *args,
 	uint32_t shader_rec_offset = roundup(render_offset +
 					     args->render_cl_len, 16);
 	uint32_t exec_size = shader_rec_offset + args->shader_record_len;
-	uint32_t temp_size = exec_size + (sizeof(uint32_t) *
+	uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) *
 					  args->shader_record_count);
 
 	if (shader_rec_offset < render_offset ||
 	    exec_size < shader_rec_offset ||
-	    args->shader_record_count >= (UINT_MAX / sizeof(uint32_t)) ||
+	    args->shader_record_count >= (UINT_MAX /
+					  sizeof(struct vc4_shader_state)) ||
 	    temp_size < exec_size) {
 		DRM_ERROR("overflow in exec arguments\n");
 		goto fail;
diff --git a/drivers/gpu/drm/vc4/vc4_packet.h b/drivers/gpu/drm/vc4/vc4_packet.h
new file mode 100644
index 000000000000..e7c334c55569
--- /dev/null
+++ b/drivers/gpu/drm/vc4/vc4_packet.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright © 2014 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef VC4_PACKET_H
+#define VC4_PACKET_H
+
+enum vc4_packet {
+        VC4_PACKET_HALT = 0,
+        VC4_PACKET_NOP = 1,
+
+        VC4_PACKET_FLUSH = 4,
+        VC4_PACKET_FLUSH_ALL = 5,
+        VC4_PACKET_START_TILE_BINNING = 6,
+        VC4_PACKET_INCREMENT_SEMAPHORE = 7,
+        VC4_PACKET_WAIT_ON_SEMAPHORE = 8,
+
+        VC4_PACKET_BRANCH = 16,
+        VC4_PACKET_BRANCH_TO_SUB_LIST = 17,
+
+        VC4_PACKET_STORE_MS_TILE_BUFFER = 24,
+        VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25,
+        VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26,
+        VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27,
+        VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28,
+        VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29,
+
+        VC4_PACKET_GL_INDEXED_PRIMITIVE = 32,
+        VC4_PACKET_GL_ARRAY_PRIMITIVE = 33,
+
+        VC4_PACKET_COMPRESSED_PRIMITIVE = 48,
+        VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49,
+
+        VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56,
+
+        VC4_PACKET_GL_SHADER_STATE = 64,
+        VC4_PACKET_NV_SHADER_STATE = 65,
+        VC4_PACKET_VG_SHADER_STATE = 66,
+
+        VC4_PACKET_CONFIGURATION_BITS = 96,
+        VC4_PACKET_FLAT_SHADE_FLAGS = 97,
+        VC4_PACKET_POINT_SIZE = 98,
+        VC4_PACKET_LINE_WIDTH = 99,
+        VC4_PACKET_RHT_X_BOUNDARY = 100,
+        VC4_PACKET_DEPTH_OFFSET = 101,
+        VC4_PACKET_CLIP_WINDOW = 102,
+        VC4_PACKET_VIEWPORT_OFFSET = 103,
+        VC4_PACKET_Z_CLIPPING = 104,
+        VC4_PACKET_CLIPPER_XY_SCALING = 105,
+        VC4_PACKET_CLIPPER_Z_SCALING = 106,
+
+        VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112,
+        VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113,
+        VC4_PACKET_CLEAR_COLORS = 114,
+        VC4_PACKET_TILE_COORDINATES = 115,
+        GEM_HANDLES = 254,
+} __attribute__ ((__packed__));
+
+/** @{
+ * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL (low bits of the
+ * address)
+ */
+
+#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_VG_MASK_DUMP (1 << 2)
+#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_ZS_DUMP      (1 << 1)
+#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_COLOR_DUMP   (1 << 0)
+
+/** @} */
+
+/** @{ byte 1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL */
+#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 7)
+#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     (1 << 6)
+#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  (1 << 5)
+#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         (1 << 4)
+
+#define VC4_STORE_TILE_BUFFER_RGBA8888             (0 << 0)
+#define VC4_STORE_TILE_BUFFER_BGR565_DITHER        (1 << 0)
+#define VC4_STORE_TILE_BUFFER_BGR565               (2 << 0)
+/** @} */
+
+/** @{ byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL */
+#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0         (0 << 6)
+#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4     (1 << 6)
+#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16    (2 << 6)
+
+#define VC4_STORE_TILE_BUFFER_FORMAT_RASTER        (0 << 4)
+#define VC4_STORE_TILE_BUFFER_FORMAT_T             (1 << 4)
+#define VC4_STORE_TILE_BUFFER_FORMAT_LT            (2 << 4)
+
+#define VC4_STORE_TILE_BUFFER_NONE                 (0 << 0)
+#define VC4_STORE_TILE_BUFFER_COLOR                (1 << 0)
+#define VC4_STORE_TILE_BUFFER_ZS                   (2 << 0)
+#define VC4_STORE_TILE_BUFFER_Z                    (3 << 0)
+#define VC4_STORE_TILE_BUFFER_VG_MASK              (4 << 0)
+#define VC4_STORE_TILE_BUFFER_FULL                 (5 << 0)
+/** @} */
+
+/* This flag is only present in NV shader state. */
+#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS         (1 << 3)
+#define VC4_SHADER_FLAG_ENABLE_CLIPPING            (1 << 2)
+#define VC4_SHADER_FLAG_VS_POINT_SIZE              (1 << 1)
+#define VC4_SHADER_FLAG_FS_SINGLE_THREAD           (1 << 0)
+
+/** @{ byte 2 of config bits. */
+#define VC4_CONFIG_BITS_EARLY_Z_UPDATE             (1 << 1)
+#define VC4_CONFIG_BITS_EARLY_Z                    (1 << 0)
+/** @} */
+
+/** @{ byte 1 of config bits. */
+#define VC4_CONFIG_BITS_Z_UPDATE                   (1 << 7)
+/** same values in this 3-bit field as PIPE_FUNC_* */
+#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT           4
+#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE        (1 << 3)
+
+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO    (0 << 1)
+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD        (1 << 1)
+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR         (2 << 1)
+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO       (3 << 1)
+
+#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT       (1 << 0)
+/** @} */
+
+/** @{ byte 0 of config bits. */
+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6)
+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X   (1 << 6)
+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X  (2 << 6)
+
+#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES        (1 << 4)
+#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET        (1 << 3)
+#define VC4_CONFIG_BITS_CW_PRIMITIVES              (1 << 2)
+#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK           (1 << 1)
+#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT          (1 << 0)
+/** @} */
+
+/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */
+#define VC4_BIN_CONFIG_DB_NON_MS                   (1 << 7)
+
+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32         (0 << 5)
+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64         (1 << 5)
+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128        (2 << 5)
+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256        (3 << 5)
+
+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32    (0 << 3)
+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64    (1 << 3)
+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128   (2 << 3)
+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256   (3 << 3)
+
+#define VC4_BIN_CONFIG_AUTO_INIT_TSDA              (1 << 2)
+#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT           (1 << 1)
+#define VC4_BIN_CONFIG_MS_MODE_4X                  (1 << 0)
+/** @} */
+
+/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */
+#define VC4_RENDER_CONFIG_DB_NON_MS                (1 << 12)
+#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11)
+#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G      (1 << 10)
+#define VC4_RENDER_CONFIG_COVERAGE_MODE            (1 << 9)
+#define VC4_RENDER_CONFIG_ENABLE_VG_MASK           (1 << 8)
+
+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_LINEAR     (0 << 6)
+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_T          (1 << 6)
+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_LT         (2 << 6)
+
+#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X         (0 << 4)
+#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X         (1 << 4)
+#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X        (2 << 4)
+
+#define VC4_RENDER_CONFIG_FORMAT_BGR565            (0 << 2)
+#define VC4_RENDER_CONFIG_FORMAT_RGBA8888          (1 << 2)
+#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED   (2 << 2)
+
+#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT        (1 << 1)
+#define VC4_RENDER_CONFIG_MS_MODE_4X               (1 << 0)
+
+#endif /* VC4_PACKET_H */
diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
index 438e2257a64b..cb1c67e061f2 100644
--- a/drivers/gpu/drm/vc4/vc4_validate.c
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
@@ -40,6 +40,7 @@
  */
 
 #include "vc4_drv.h"
+#include "vc4_packet.h"
 #include "vc4_regs.h"
 
 #define VALIDATE_ARGS \
@@ -125,12 +126,11 @@ validate_gl_shader_state(VALIDATE_ARGS)
 		return -EINVAL;
 	}
 
-	exec->shader_state[i] = *(uint32_t *)untrusted;
-	if (exec->shader_state[i] & 15) {
-		DRM_ERROR("shader record must by 16-byte aligned\n");
-		return -EINVAL;
-	}
-	*(uint32_t *)validated = exec->shader_state[i] + exec->shader_paddr;
+	exec->shader_state[i].packet = VC4_PACKET_GL_SHADER_STATE;
+	exec->shader_state[i].addr = *(uint32_t *)untrusted;
+
+	*(uint32_t *)validated = exec->shader_state[i].addr +
+		exec->shader_paddr;
 
 	return 0;
 }
@@ -145,9 +145,17 @@ validate_nv_shader_state(VALIDATE_ARGS)
 		return -EINVAL;
 	}
 
-	/* XXX: validate alignment */
-	exec->shader_state[i] = *(uint32_t *)untrusted;
-	*(uint32_t *)validated = exec->shader_state[i] + exec->shader_paddr;
+	exec->shader_state[i].packet = VC4_PACKET_NV_SHADER_STATE;
+	exec->shader_state[i].addr = *(uint32_t *)untrusted;
+
+	if (exec->shader_state[i].addr & 15) {
+		DRM_ERROR("NV shader state address 0x%08x misaligned\n",
+			  exec->shader_state[i].addr);
+		return -EINVAL;
+	}
+
+	*(uint32_t *)validated =
+		exec->shader_state[i].addr + exec->shader_paddr;
 
 	return 0;
 }
@@ -343,6 +351,81 @@ vc4_validate_cl(struct drm_device *dev,
 	return 0;
 }
 
+static int
+validate_shader_rec(struct drm_device *dev,
+		    struct exec_info *exec,
+		    void *validated,
+		    void *unvalidated,
+		    uint32_t len,
+		    struct vc4_shader_state *state)
+{
+	uint32_t *src_handles = unvalidated;
+	void *src_pkt;
+	void *dst_pkt = validated;
+	static const int gl_bo_offsets[] = {
+		4, 8, /* fs code, ubo */
+		16, 20, /* vs code, ubo */
+		28, 32, /* cs code, ubo */
+	};
+	static const int nv_bo_offsets[] = {
+		4, 8, /* fs code, ubo */
+		12, /* vbo */
+	};
+	struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_bo_offsets) + 8];
+	const int *bo_offsets;
+	uint32_t nr_attributes = 0, nr_bo, packet_size;
+	int i;
+
+	if (state->packet == VC4_PACKET_NV_SHADER_STATE) {
+		bo_offsets = nv_bo_offsets;
+		nr_bo = ARRAY_SIZE(nv_bo_offsets);
+
+		packet_size = 16;
+	} else {
+		bo_offsets = gl_bo_offsets;
+		nr_bo = ARRAY_SIZE(gl_bo_offsets);
+
+		nr_attributes = state->addr & 0x7;
+		if (nr_attributes == 0)
+			nr_attributes = 8;
+		packet_size = 36 + nr_attributes * 8;
+	}
+	if ((nr_bo + nr_attributes) * 4 + packet_size > len) {
+		DRM_ERROR("overflowed shader packet read "
+			  "(handles %d, packet %d, len %d)\n",
+			  (nr_bo + nr_attributes) * 4, packet_size, len);
+		return -EINVAL;
+	}
+
+	src_pkt = unvalidated + 4 * (nr_bo + nr_attributes);
+	memcpy(dst_pkt, src_pkt, packet_size);
+
+	for (i = 0; i < nr_bo + nr_attributes; i++) {
+		if (src_handles[i] >= exec->bo_count) {
+			DRM_ERROR("shader rec bo index %d > %d\n",
+				  src_handles[i], exec->bo_count);
+			return -EINVAL;
+		}
+		bo[i] = exec->bo[src_handles[i]];
+	}
+
+	for (i = 0; i < nr_bo; i++) {
+		/* XXX: validation */
+		uint32_t o = bo_offsets[i];
+		*(uint32_t *)(dst_pkt + o) =
+			bo[i]->paddr + *(uint32_t *)(src_pkt + o);
+	}
+
+	for (i = 0; i < nr_attributes; i++) {
+		/* XXX: validation */
+		uint32_t o = 36 + i * 8;
+		*(uint32_t *)(dst_pkt + o) =
+			bo[nr_bo + i]->paddr + *(uint32_t *)(src_pkt + o);
+	}
+
+	return 0;
+}
+
 int
 vc4_validate_shader_recs(struct drm_device *dev,
 			 void *validated,
@@ -353,54 +436,31 @@ vc4_validate_shader_recs(struct drm_device *dev,
 	uint32_t dst_offset = 0;
 	uint32_t src_offset = 0;
 	uint32_t i;
+	int ret = 0;
 
-	/* Look, all I'm doing here is relocating the one packet in
-	 * phire's hackdriver code.
-	 */
 	for (i = 0; i < exec->shader_state_count; i++) {
-		/* XXX: lots of overflow */
-		uint32_t *src_handles = unvalidated + src_offset;
-		void *src_pkt = &src_handles[3];
-		void *dst_pkt = validated + dst_offset;
-		uint32_t fs_code_index = src_handles[0];
-		uint32_t fs_uniform_index = src_handles[1];
-		uint32_t vbo_index = src_handles[2];
-		struct drm_gem_cma_object *fs_code_bo, *fs_uniform_bo, *vbo;
-
-		if (fs_code_index >= exec->bo_count) {
-			DRM_ERROR("FS index %d > %d\n",
-				  fs_code_index, exec->bo_count);
-			return -EINVAL;
-		}
-		if (fs_uniform_index >= exec->bo_count) {
-			DRM_ERROR("FS index %d > %d\n",
-				  fs_uniform_index, exec->bo_count);
-			return -EINVAL;
-		}
-		if (vbo_index >= exec->bo_count) {
-			DRM_ERROR("FS index %d > %d\n",
-				  vbo_index, exec->bo_count);
+		if ((exec->shader_state[i].addr & ~0xf) !=
+		    (validated - exec->exec_bo->vaddr -
+		     (exec->shader_paddr - exec->exec_bo->paddr))) {
+			DRM_ERROR("unexpected shader rec offset: "
+				  "0x%08x vs 0x%08x\n",
+				  exec->shader_state[i].addr & ~0xf,
+				  (int)(validated -
+                                        exec->exec_bo->vaddr -
+                                        (exec->shader_paddr -
+                                         exec->exec_bo->paddr)));
 			return -EINVAL;
 		}
 
-		if (src_offset + len >
-		    src_pkt + 16 - unvalidated) {
-			DRM_ERROR("weird overflow of src data\n");
-			return -EINVAL;
-		}
-
-		fs_code_bo = exec->bo[fs_code_index];
-		fs_uniform_bo = exec->bo[fs_uniform_index];
-		vbo = exec->bo[vbo_index];
-
-		memcpy(dst_pkt, src_pkt, 16);
-		*(uint32_t *)(dst_pkt + 4) =
-			fs_code_bo->paddr + *(uint32_t *)(src_pkt + 4);
-		*(uint32_t *)(dst_pkt + 8) =
-			fs_uniform_bo->paddr + *(uint32_t *)(src_pkt + 8);
-		*(uint32_t *)(dst_pkt + 12) =
-			vbo->paddr + *(uint32_t *)(src_pkt + 12);
+		ret = validate_shader_rec(dev, exec,
+					  validated + dst_offset,
+					  unvalidated + src_offset,
+					  len - src_offset,
+					  &exec->shader_state[i]);
+		if (ret)
+			return ret;
+		/* XXX: incr dst/src offset */
 	}
 
-	return 0;
+	return ret;
 }