drm/vc4: Improve support for load/store tile buffers

Signed-off-by: Eric Anholt <eric@anholt.net>

2 files changed, 40 insertions, 28 deletions

diff --git a/drivers/gpu/drm/vc4/vc4_packet.h b/drivers/gpu/drm/vc4/vc4_packet.h
index e7c334c55569..cc3786677782 100644
--- a/drivers/gpu/drm/vc4/vc4_packet.h
+++ b/drivers/gpu/drm/vc4/vc4_packet.h
@@ -76,44 +76,56 @@ enum vc4_packet {
 } __attribute__ ((__packed__));
 
 /** @{
- * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL (low bits of the
- * address)
+ *
+ * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address)
  */
 
-#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_VG_MASK_DUMP (1 << 2)
-#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_ZS_DUMP      (1 << 1)
-#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_COLOR_DUMP   (1 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2)
+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS      (1 << 1)
+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR   (1 << 0)
 
 /** @} */
 
-/** @{ byte 1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL */
+/** @{
+ *
+ * byte 1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
+ */
 #define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 7)
 #define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     (1 << 6)
 #define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  (1 << 5)
 #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         (1 << 4)
 
-#define VC4_STORE_TILE_BUFFER_RGBA8888             (0 << 0)
-#define VC4_STORE_TILE_BUFFER_BGR565_DITHER        (1 << 0)
-#define VC4_STORE_TILE_BUFFER_BGR565               (2 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888         (0 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER    (1 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_BGR565           (2 << 0)
 /** @} */
 
-/** @{ byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL */
+/** @{
+ *
+ * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
+ */
 #define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0         (0 << 6)
 #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4     (1 << 6)
 #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16    (2 << 6)
 
-#define VC4_STORE_TILE_BUFFER_FORMAT_RASTER        (0 << 4)
-#define VC4_STORE_TILE_BUFFER_FORMAT_T             (1 << 4)
-#define VC4_STORE_TILE_BUFFER_FORMAT_LT            (2 << 4)
+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_RASTER    (0 << 4)
+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_T         (1 << 4)
+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_LT        (2 << 4)
 
-#define VC4_STORE_TILE_BUFFER_NONE                 (0 << 0)
-#define VC4_STORE_TILE_BUFFER_COLOR                (1 << 0)
-#define VC4_STORE_TILE_BUFFER_ZS                   (2 << 0)
-#define VC4_STORE_TILE_BUFFER_Z                    (3 << 0)
-#define VC4_STORE_TILE_BUFFER_VG_MASK              (4 << 0)
-#define VC4_STORE_TILE_BUFFER_FULL                 (5 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_NONE             (0 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_COLOR            (1 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_ZS               (2 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_Z                (3 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK          (4 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_FULL             (5 << 0)
 /** @} */
 
+#define VC4_INDEX_BUFFER_U8                        (0 << 4)
+#define VC4_INDEX_BUFFER_U16                       (1 << 4)
+
 /* This flag is only present in NV shader state. */
 #define VC4_SHADER_FLAG_SHADED_CLIP_COORDS         (1 << 3)
 #define VC4_SHADER_FLAG_ENABLE_CLIPPING            (1 << 2)
diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
index cb1c67e061f2..a68d331f0497 100644
--- a/drivers/gpu/drm/vc4/vc4_validate.c
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
@@ -64,19 +64,17 @@ validate_branch_to_sublist(VALIDATE_ARGS)
 }
 
 static int
-validate_store_tile_buffer_general(VALIDATE_ARGS)
+validate_loadstore_tile_buffer_general(VALIDATE_ARGS)
 {
-	struct drm_gem_cma_object *fbo;
+	uint32_t packet_b0 = *(uint8_t *)(untrusted + 0);
+	struct drm_gem_cma_object *fbo = exec->bo[exec->bo_index[0]];
 
-	/* XXX: Validate address offset */
+	if ((packet_b0 & 0xf) == VC4_LOADSTORE_TILE_BUFFER_NONE)
+		return 0;
 
-	fbo = exec->bo[exec->bo_index[0]];
-
-	/* XXX */
-	/*
+	/* XXX: Validate address offset */
 	*(uint32_t *)(validated + 2) =
 		*(uint32_t *)(untrusted + 2) + fbo->paddr;
-		*/
 
 	return 0;
 }
@@ -230,7 +228,9 @@ static const struct cmd_info {
 	[25] = { 0, 1, 1, "store MS resolved tile color buffer and EOF", NULL },
 
 	[28] = { 0, 1, 7, "Store Tile Buffer General",
-		 validate_store_tile_buffer_general },
+		 validate_loadstore_tile_buffer_general },
+	[29] = { 0, 1, 7, "Load Tile Buffer General",
+		 validate_loadstore_tile_buffer_general },
 
 	[32] = { 1, 1, 14, "Indexed Primitive List",
 		 validate_indexed_prim_list },