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| author | Eric Anholt <eric@anholt.net> | 2014-09-18 17:49:10 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2015-06-04 14:15:19 -0700 |
| commit | dcced03bd1272b9633152daae38cc500afd3d5ff (patch) | |
| tree | 55289991150598532234fc082087239ec83b1bac | |
| parent | 680af4ecbc4ac8606105c9e42308897641f5ea9a (diff) | |
| download | linux-dcced03bd1272b9633152daae38cc500afd3d5ff.tar.gz | |
drm/vc4: Allow stencil uniform setup.
Nothing in this register affects memory access, just how writes impact
the tile buffer.
Signed-off-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_validate_shaders.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c index f7f35cebd228..708c4fe864cb 100644 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c @@ -152,7 +152,6 @@ check_register_write(struct vc4_validated_shader_info *validated_shader, case QPU_W_HOST_INT: case QPU_W_TMU_NOSWAP: - case QPU_W_TLB_STENCIL_SETUP: case QPU_W_TLB_ALPHA_MASK: case QPU_W_MUTEX_RELEASE: /* XXX: I haven't thought about these, so don't support them @@ -172,6 +171,9 @@ check_register_write(struct vc4_validated_shader_info *validated_shader, * triggered by QPU_W_VPM_ADDR writes. */ return true; + + case QPU_W_TLB_STENCIL_SETUP: + return true; } return true; |