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| author | Eric Anholt <eric@anholt.net> | 2015-05-29 15:05:51 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2015-06-04 14:15:37 -0700 |
| commit | fa1ad658e659f0a0f1f056d0dd131aad5d0167c6 (patch) | |
| tree | a0c1d5659bef9776d9a96627974cbefac23f89a0 | |
| parent | 4deff3653db719f62834ca866e818dbe5d403afe (diff) | |
| download | linux-fa1ad658e659f0a0f1f056d0dd131aad5d0167c6.tar.gz | |
drm/vc4: Don't bother flushing the ARM CPU caches on GEM exec.
All of our BOs are mapped write-combining both in the kernel and
userspace by drm_gem_cma_helper.c, so anything we've written will end
up in main memory, anyway. The only coherency trouble we might have
would be if we had content in the CPU's write combining buffers that
hadn't been flushed, but a CPU cache flush is unlikely to help with
that, anyway.
Improves no-swapbuffers drawarrays-mode isosurf performance by around 20%.
Signed-off-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_gem.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c index 17d15df285fd..2aad41118cec 100644 --- a/drivers/gpu/drm/vc4/vc4_gem.c +++ b/drivers/gpu/drm/vc4/vc4_gem.c @@ -180,14 +180,6 @@ vc4_flush_caches(struct drm_device *dev) VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); - - /* Flush the CPU L1/L2 caches. Since the GPU reads from L3 - * don't snoop up the L1/L2, we have to either do this or - * manually clflush the cachelines we (and userspace) dirtied. - */ - flush_cache_all(); - - barrier(); } /* Sets the registers for the next job to be actually be executed in |