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author | Olof Johansson <olof@lixom.net> | 2013-06-25 13:43:28 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2013-06-25 13:43:28 -0700 |
commit | 37c5a9f7d73352650447c3984a39007304287303 (patch) | |
tree | 67b00299aa0e2bbe9b879ad957eff17bfed72e4e /arch/arm/boot/dts/stih41x.dtsi | |
parent | 2655e828350cc7558d1a74cd4464e34b81e17f36 (diff) | |
parent | 40e3e6725370481b7b81d969dbde056f50d870ae (diff) | |
download | linux-37c5a9f7d73352650447c3984a39007304287303.tar.gz |
Merge branch 'sti/soc' into next/late
From Srinivas Kandagatla <srinivas.kandagatla@st.com>:
This patch-set adds basic support for STMicroelectronics STi series SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU, designed for
use in Set-top-boxes. The SOC support is available in mach-sti which
contains support code for STiH415, STiH416 SOCs including the generic
board support.
The reason for adding two SOCs at this patch set is to show that no new
C code is required for second SOC(STiH416) support.
* sti/soc:
ARM: stih41x: Add B2020 board support
ARM: stih41x: Add B2000 board support
ARM: sti: Add DEBUG_LL console support
ARM: sti: Add STiH416 SOC support
ARM: sti: Add STiH415 SOC support
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/stih41x.dtsi')
-rw-r--r-- | arch/arm/boot/dts/stih41x.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi new file mode 100644 index 000000000000..7321403cab8a --- /dev/null +++ b/arch/arm/boot/dts/stih41x.dtsi @@ -0,0 +1,38 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + intc: interrupt-controller@fffe1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffe1000 0x1000>, + <0xfffe0100 0x100>; + }; + + scu@fffe0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffe0000 0x1000>; + }; + + timer@fffe0200 { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffe0200 0x100>; + interrupts = <1 11 0x04>; + clocks = <&arm_periph_clk>; + }; +}; |