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| author | Jacky Bai <ping.bai@nxp.com> | 2021-09-14 14:52:05 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2021-09-30 16:22:56 +0300 |
| commit | ae8a10d697cd771fb6d28d55c78d1a75b4a4152e (patch) | |
| tree | 822df297b7db776249ab2710409191c4215f76c2 /drivers/clk/uniphier/clk-uniphier-sys.c | |
| parent | 75c6f1a0191a8d0c5c8e9cc5d33daa47d88783e1 (diff) | |
| download | linux-ae8a10d697cd771fb6d28d55c78d1a75b4a4152e.tar.gz | |
clk: imx: disable the pfd when set pfdv2 clock rate
It is possible that a PFD is enabled in HW but not in SW. That
means the enable count & prepare count of the PFD clock is '0',
so the 'CLK_SET_RATE' flag can do nothing when the rate is changed
while the PFD is hw enabled. In order to safely change the pfd
rate, we can disable the PFD directly if it is hw enabled but not
used by SW end user.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210914065208.3582128-7-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/uniphier/clk-uniphier-sys.c')
0 files changed, 0 insertions, 0 deletions