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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-10-09175-3012/+50942
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS update from Ralf Baechle: "This is the MIPS update for 3.7. A fair chunk of them are platform updates to the Cavium Octeon SOC (which involves machine generated header files of considerable size), Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx platforms. Support for the commercial MIPS simulator MIPSsim has been removed as MIPS Technologies is shifting away from this product and Qemu is offering various more powerful platforms. The generic MIPS code can now also probe for no-execute / write-only TLB features implemented without the full SmartMIPS extension as permitted by the latest MIPS processor architecture. Lots of small changes to generic code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits) MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x MIPS: BCM63XX: Properly handle mac address octet overflow MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user. MIPS: Replace `-' in defconfig filename wth `_' for consistency. MIPS: Wire kcmp syscall. MIPS: MIPSsim: Remove the MIPSsim platform. MIPS: NOTIFY_RESUME is not needed in TIF masks MIPS: Merge the identical "return from syscall" per-ABI code MIPS: Unobfuscate _TIF..._MASK MIPS: Prevent hitting do_notify_resume() with !user_mode(regs). MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. MIPS: Add base architecture support for RI and XI. MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. MIPS: uasm: Add INS and EXT instructions. MIPS: Avoid pipeline stalls on some MIPS32R2 cores. MIPS: Make VPE count to be one-based. MIPS: Add new end of interrupt functionality for GIC. MIPS: Add EIC support for GIC. MIPS: Code clean-ups for the GIC. ...
| * Merge branch 'master' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-10-0524-251/+1045
| |\ | | | | | | | | | mips-for-linux-next
| | * MIPS: BCM63XX: remove bogus ENETSW_TXDMA interrupts from BCM6328Jonas Gorski2012-08-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were erroneously copied from BCM6368. BCM6328 does not expose the ENETSW_TXDMA interrupts, and BCM_6328_HIGH_IRQ_BASE + 7 is actually used for the second UART. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4090/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: BCM63XX: use a switch for external irq configMaxime Bizon2012-08-241-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes the code a bit more readable and easier to add support for new chips. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4093/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: BCM63XX: don't write to the chipid register on rebootMaxime Bizon2012-08-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | While harmless, it is bad style to do so. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4092/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: BCM63XX: add external irq support for BCM6345Maxime Bizon2012-08-243-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing definitions for BCM6345. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4091/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * spi: Add SPI master controller for OCTEON SOCs.David Daney2012-08-224-0/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the driver, link it into the kbuild system and provide device tree binding documentation. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: http://patchwork.linux-mips.org/patch/4292/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: OCTEON: Add register definitions for SPI host hardware.David Daney2012-08-221-0/+328
| | | | | | | | | | | | | | | | | | | | | | | | Needed by SPI driver. Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/3796/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: Fix build error for non-malta VSMP kernelAnoop P A2012-08-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VSMP kernel build for non-malta platforms fails with following error LD init/built-in.o LD .tmp_vmlinux1 arch/mips/built-in.o: In function `vsmp_init_secondary': smp-mt.c:(.cpuinit.text+0x23cc): undefined reference to `gic_present' smp-mt.c:(.cpuinit.text+0x23d0): undefined reference to `gic_present' make: *** [.tmp_vmlinux1] Error 1 gic_present variable is declared only if IRQ_GIC is selected. Signed-off-by: Anoop P A <anoop.pa@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/2039/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: introduce CPU_R4K_CACHE_TLBFlorian Fainelli2012-08-222-16/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: introduce CPU_R4K_FPUFlorian Fainelli2012-08-222-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | R4K-style CPUs have this boolean defined by default. Allows us to remove some lines in arch/mips/kernel/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3330/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: introduce CPU_GENERIC_DUMP_TLBFlorian Fainelli2012-08-222-20/+5
| | | | | | | | | | | | | | | | | | | | | | | | Allows us not to duplicate more lines in arch/mips/lib/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3329/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: Netlogic: XLP defconfig updateJayachandran C2012-08-221-43/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable more devices and options for XLP default configuration: - Serial ports from FDT - NOR Flash support and partitions from FDT - PCI and PCI bus support and devices - SATA, e1000e, sky2 - I2C ocores controller and devices - ds1374, lm90 - Misc options such as RTC, partition formats etc. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
| | * MIPS: Netlogic: Add support for built in DTBJayachandran C2012-08-225-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a config option to embed a device tree for XLP evaluation boards. This DTB will be used if the firmware does not pass in a device tree pointer. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Patchwork: http://patchwork.linux-mips.org/patch/4103/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: Netlogic: Move serial ports to device treeJayachandran C2012-08-223-109/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the serial ports to the device tree and remove the platform code for adding them. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Patchwork: http://patchwork.linux-mips.org/patch/4098/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: Netlogic: DTS file for XLP boardsGanesan Ramalingam2012-08-221-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a basic DTS file netlogic/dts/nlm_xlp.dts which contains memory, i2c devices, NOR flash and command line arguments. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Patchwork: http://patchwork.linux-mips.org/patch/4100/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: Netlogic: merge of.c into setup.cJayachandran C2012-08-223-35/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the function device_tree_init() from netlogic/xlp/of.c to setup.c, and remove the wrapper functions reserve_mem_mach() and free_mem_mach(). Remove file netlogic/xlp/of.c, and the Makefile entry for it. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Patchwork: http://patchwork.linux-mips.org/patch/4097/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * MIPS: lantiq: explicitly enable clkout generationJohn Crispin2012-08-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Previously we relied on the bootloader to have enabled this bit. However some bootloaders seem to not enable this for us. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4120/
| * | MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLsGabor Juhos2012-10-012-28/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Besides the CPU and DDR PLLs, the CPU and DDR frequencies can be derived from other PLLs in the SRIF block on the AR934x SoCs. The current code does not checks if the SRIF PLLs are used and this can lead to incorrectly calculated CPU/DDR frequencies. Fix it by calculating the frequencies from SRIF PLLs if those are used on a given board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: <stable@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4324/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934xGabor Juhos2012-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current dividers in the code are wrong and this leads to broken CPU frequency calculation on boards where the fractional part is used. For example, if the SoC is running from a 40MHz reference clock, refdiv=1, nint=14, outdiv=0 and nfrac=31 the real frequency is 579.375MHz but the current code calculates 569.687MHz instead. Because the system time is indirectly related to the CPU frequency the broken computation causes drift in the system time. The correct divider is 2^6 for the CPU PLL and 2^10 for the DDR PLL. Use the correct values to fix the issue. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4305/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: BCM63XX: Properly handle mac address octet overflowJonas Gorski2012-10-011-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While calculating the mac address the pointer for the current octet was never reset back to the least significant one after being decremented because of an octet overflow. This resulted in the code continuing to increment at the current octet, potentially generating duplicate or invalid mac addresses. As a second issue the pointer was allowed to advance up to the most significant octet, modifying the OUI, and potentially changing the type of mac address. Rewrite the code so it resets the pointer to the least significant in each outer loop step, and bails out when the least significant octet of the OUI is reached. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Patchwork: https://patchwork.linux-mips.org/patch/4348/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.Jonas Gorski2012-10-011-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | b01da9f1 ("MIPS: Prune some target specific code out of prom.c") removed the generic implementation of device_tree_init, breaking the kernel build when manually selecting USE_OF. Hide the config symbol so it can't be selected acidentially anymore. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/4346/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | Merge branch 'ralf-3.7' of ↵Ralf Baechle2012-09-2844-116/+2874
| |\ \ | | | | | | | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| | * | MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.Steven J. Hill2012-09-131-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The EXT and INS instructions can be used to decrease code size and thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: uasm: Add INS and EXT instructions.Steven J. Hill2012-09-132-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These are MIPS32R2 instructions for merging and extracting bit fields from one GPR into another. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Avoid pipeline stalls on some MIPS32R2 cores.Steven J. Hill2012-09-131-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture specification says that an EHB instruction is needed to avoid a hazard when writing TLB entries. However, some cores do not have this hazard, and thus the EHB instruction causes a costly pipeline stall. Detect these cores and do not use the EHB instruction. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Make VPE count to be one-based.Steven J. Hill2012-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When dealing with multiple VPEs, the count needs to be one-based for correct initialization of the GIC. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Add new end of interrupt functionality for GIC.Steven J. Hill2012-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Each platform should define its own 'gic_finish_irq' function. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Add EIC support for GIC.Steven J. Hill2012-09-132-8/+95
| | | | | | | | | | | | | | | | | | | | | | | | Add support to use an external interrupt controller with the GIC. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Code clean-ups for the GIC.Steven J. Hill2012-09-132-34/+26
| | | | | | | | | | | | | | | | | | | | | | | | Fix whitespace, beautify the code and remove debug statements. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Make GIC code platform independent.Steven J. Hill2012-09-134-72/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC interrupt code is used by multiple platforms and the current code was half Malta dependent code. These changes abstract away the platform specific differences. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Changes to configuration files for SEAD-3 platform.Steven J. Hill2012-09-133-2/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change MIPS configuration files to add the SEAD-3. Also add new default configuration file for a SEAD-3 kernel. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Add core files for MIPS SEAD-3 development platform.Steven J. Hill2012-09-1329-0/+2445
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com>
| | * | MIPS: Add support for the 1074K core.Steven J. Hill2012-09-134-0/+28
| | |/ | | | | | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * | Merge branch 'rixi-3.7' of ↵Ralf Baechle2012-09-2811-29/+35
| |\ \ | | | | | | | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| | * | MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-138-29/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
| | * | MIPS: Add base architecture support for RI and XI.Steven J. Hill2012-09-134-1/+10
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
| * | Merge branch 'broadcom' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-09-2710-39/+401
| |\ \ | | | | | | | | | | | | mips-for-linux-next
| | * | MIPS: BCM63XX: Create platform_device for USBDKevin Cernekee2012-08-305-1/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Reviewed-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4111/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 deviceKevin Cernekee2012-08-302-1/+221
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4084/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: BCM63XX: Fix USB IRQ definitions for 6328Kevin Cernekee2012-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OHCI/EHCI are in the high (second) word. Not currently used by any driver. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4026/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: BCM63XX: Add register definitions for USBD dependenciesKevin Cernekee2012-08-302-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB 2.0 device depends on some functionality in other blocks, such as GPIO and USBH. Add those register definitions here. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4025/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: BCM63XX: Add new IUDMA definitions needed for USBDKevin Cernekee2012-08-302-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4083/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: BCM63XX: Move DMA descriptor definition into common header fileKevin Cernekee2012-08-302-29/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "IUDMA" engine used by bcm63xx_enet is also used by other blocks, such as the USB 2.0 device. Move the definitions into a common file so that they do not need to be duplicated in each driver. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4082/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: BCM63XX: Expose the USBH/USBD clocks on BCM6328/BCM6368Kevin Cernekee2012-08-301-1/+20
| | |/ | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4022/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | Merge branch 'ath79' of git://dev.phrozen.org/mips-next into mips-for-linux-nextRalf Baechle2012-09-2799-555/+671
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| | * | MIPS: ath79: register USB host controller on the DB120 boardGabor Juhos2012-08-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4173/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: ath79: add USB platform setup code for AR934XGabor Juhos2012-08-282-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4172/ Signed-off-by: John Crispin <blogic@openwrt.org>
| | * | MIPS: ath79: use a helper function for USB resource initializationGabor Juhos2012-08-281-36/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This improves code readability, and ensures that all resource fields will be initialized correctly. Additionally, it helps to reduce the size of the kernel image by using uninitialized resource variables. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4171/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | | Merge branch 'lantiq' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-09-2722-221/+2272
| |\ \ \ | | | | | | | | | | | | | | | mips-for-linux-next
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