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* ARM: dts: Renesas R9A06G032 SMP enable methodMichel Pollet2018-07-231-0/+2
| | | | | | | | | Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: Renesas R9A06G032 base device tree fileMichel Pollet2018-07-231-0/+113
This adds the Renesas R9A06G032 bare bone support. This currently only handles the SYSCTRL block note, generic parts (gic, architected timer) and a UART. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: updated MAINTAINERS file [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>