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*-. Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', ↵Stephen Boyd2019-03-081-0/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-mtk-crit' and 'clk-mtk' into clk-next * clk-ingenic: clk: ingenic: Remove set but not used variable 'enable' clk: ingenic: Fix doc of ingenic_cgu_div_info clk: ingenic: Fix round_rate misbehaving with non-integer dividers clk: ingenic: jz4740: Fix gating of UDC clock * clk-mtk-mux: clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 * clk-qcom-sdm845-pcie: clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks * clk-mtk-crit: clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro * clk-mtk: clk: mediatek: correct cpu clock name for MT8173 SoC
| | * clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocksBjorn Andersson2019-02-261-0/+5
| |/ | | | | | | | | | | | | | | The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the PHY, describe this relationship. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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*-. \ Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ↵Stephen Boyd2019-03-0810-53/+142
|\ \ \ | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-SA-fixes' into clk-next - Updates for qcom MSM8998 GCC clks - qcom MSM8998 RPM managed clks - Random static analysis fixes for clk drivers * clk-qcom-msm8998: clk: qcom: Make common clk_hw registrations clk: qcom: smd: Add support for MSM8998 rpm clocks clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998 clk: qcom: Add missing freq for usb30_master_clk on 8998 clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks * clk-fractional-parent: clk: fractional-divider: check parent rate only if flag is set * clk-x86-mv: clk: x86: Move clk-lpss.h to platform_data/x86 * clk-SA-fixes: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings clk: qoriq: Improve an error message
| * | clk: qcom: Make common clk_hw registrationsJeffrey Hugo2019-02-229-52/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several clock controller drivers define a list of clk_hw devices, and then register those devices in probe() before using common code to process the rest of initialization. Extend the common code to accept a list of clk_hw devices to process, thus eliminating many duplicate implementations. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Suggested-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: qcom: smd: Add support for MSM8998 rpm clocksJeffrey Hugo2019-01-091-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998 for clients to vote on. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998Jeffrey Hugo2019-01-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by the phy during init. The clock needs to be enabled during the init sequence, but may not be fully active until after the init sequence is complete. This causes a catch-22 if the clock status is checked during enable. As a result, skip the checks to avoid the troubling situation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: qcom: Add missing freq for usb30_master_clk on 8998Jeffrey Hugo2019-01-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The usb30_master_clk supports a 60Mhz frequency, but that is missing from the table of supported frequencies. Add it. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocksJeffrey Hugo2019-01-091-0/+48
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A branch clock is basically a clock that can be gated for power savings, but is also what devices/drivers consume. Configuring a branch clock's rate needs to be done at the source, so for all branch clocks which have a defined parent, set CLK_SET_RATE_PARENT so that clk_set_rate() calls on branch clocks can do what is expected. This is important as most drivers do not check the resulting clock rate after a successful clk_set_rate() call, thus the driver may get out of sync with the actual hardware state and weird issues might crop up. This has been observed with issues getting SDHCI to reliably support "fast" cards such as SDR104. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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*---. \ Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', ↵Stephen Boyd2019-03-084-13/+163
|\ \ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next - IPA clk support on Qualcomm RPMh clk controllers - Support sleeping gpios in clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Actions Semi S500 SoC clk support * clk-qcom-rpmh: clk: qcom: clk-rpmh: Add IPA clock support * clk-gpio-sleep: clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk * clk-stm32mp1: dt-bindings: clock: remove unused definition for stm32mp1 clk: stm32mp1: fix bit width of hse_rtc divider clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag clk: stm32mp1: fix HSI divider flag clk: stm32mp1: fix mcu divider table clk: stm32mp1: set ck_csi as critical clock clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks clk: stm32mp1: parent clocks update * clk-qcom-qcs404: clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs clk: qcom: remove empty lines in clk-rcg.h * clk-actions-s500: clk: actions: Add clock driver for S500 SoC dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU clk: actions: Add configurable PLL delay
| | | * clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clockTaniya Das2019-02-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CFG/M/N/D registers are at an offset of 0x20 from the CMD register only for blsp1_uart3 clock, so add it for uart3 only. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * clk: qcom: clk-rcg2: Introduce a cfg offset for RCGsTaniya Das2019-02-212-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RCG CFG/M/N/D register base could be at a different offset than the CMD register, so introduce a cfg_offset to identify the offset with respect to the CMD RCGR register. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * clk: qcom: remove empty lines in clk-rcg.hVinod Koul2019-02-211-3/+0
| | |/ | | | | | | | | | | | | | | | | | | Remove the redundant empty lines crept in. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: qcom: clk-rpmh: Add IPA clock supportDavid Dai2019-02-211-0/+146
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The clk-rpmh driver only supports on and off RPMh clock resources. Let's extend the driver by adding support for clocks that are managed by a different type of RPMh resource known as Bus Clock Manager(BCM). The BCM is a configurable shared resource aggregator that scales performance based on a set of frequency points. The Qualcomm IP Accelerator (IPA) clock is an example of a resource that is managed by the BCM and this a requirement from the IPA driver in order to scale its core clock. Signed-off-by: David Dai <daidavid1@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc: Use active only source for CPUSS clocksTaniya Das2019-01-241-4/+10
| | | | | | | | | | | | | | | | | | | | | | The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL clock and needs to vote on the active only source of XO, so as to keep the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has the same requirement. Signed-off-by: Taniya Das <tdas@codeaurora.org> Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: Select QCOM_GDSC with MSM_GCC_8998Marc Gonzalez2019-01-111-0/+1
|/ | | | | | | | | | | If QCOM_GDSC is disabled, gdsc_register() returns -ENOSYS, which causes gcc_msm8998_probe() to fail. Select QCOM_GDSC to solve the problem. gcc-msm8998: probe of 100000.clock-controller failed with error -38 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-fixes' into clk-nextStephen Boyd2018-12-141-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-fixes: clk: qcom: qcs404: Fix gpll0_out_main parent clk: zynqmp: Off by one in zynqmp_is_valid_clock() clk: mmp: Off by one in mmp_clk_add() clk: mvebu: Off by one bugs in cp110_of_clk_get() arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks clk: zynqmp: handle fixed factor param query error clk: qcom: gcc: Fix board clock node name clk: meson: axg: mark fdiv2 and fdiv3 as critical clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL clk: fixed-factor: fix of_node_get-put imbalance
| * clk: qcom: qcs404: Fix gpll0_out_main parentSrinivas Kandagatla2018-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | gpll0_out_main parent is cxo so fix it. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * Merge branch 'clk-protected-binding' into clk-fixesStephen Boyd2018-11-271-0/+18
| |\ | | | | | | | | | | | | | | | * clk-protected-binding: clk: qcom: Support 'protected-clocks' property dt-bindings: clk: Introduce 'protected-clocks' property
| * | clk: qcom: gcc: Fix board clock node nameVinod Koul2018-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Device tree node name are not supposed to have "_" in them so fix the node name use of xo_board to xo-board Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | | Merge branch 'clk-qcom-8998-resets' into clk-nextStephen Boyd2018-12-141-64/+207
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add resets and make Qualcomm MSM8998 GCC driver more functional * clk-qcom-8998-resets: clk: qcom: Drop unused 8998 clock clk: qcom: Leave mmss noc on for 8998 clk: qcom: Add missing msm8998 resets clk: qcom: gcc-msm8998: Add clkref clocks clk: qcom: gcc-msm8998: Disable halt check of UFS clocks clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at clk: qcom: Enumerate remaining msm8998 resets clk: qcom: Add xo dummy clk on msm8998 clk: qcom: Fix MSM8998 resets
| * | | clk: qcom: Drop unused 8998 clockJeffrey Hugo2018-12-141-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc_lpass_trig_clk is not used downstream, therefore there is no reason to expect it to be needed for clients. Let's remove it because messing with the clock has been observed to cause Linux hangs when the qdss_clk is initialized by rpmcc. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: Leave mmss noc on for 8998Jeffrey Hugo2018-12-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be disabled. Any mmss access depends on this clock, and its been observed that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is disabled. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: Add missing msm8998 resetsJeffrey Hugo2018-12-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") missed two USB2 resets. Add them. Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: gcc-msm8998: Add clkref clocksBjorn Andersson2018-12-051-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: gcc-msm8998: Disable halt check of UFS clocksBjorn Andersson2018-12-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_atBjorn Andersson2018-12-051-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disabling gcc_hmss_dvm_bus_clk and gcc_lpass_at_clk causes the board to lock up, and by that preventing the kernel to boot without clk_ignore_unused. gcc_hmss_dvm_bus_clk is marked always-on downstream, but not referenced, and gcc_lpass_at_clk isn't mentioned. So let's remove them until they are needed by some client. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: Enumerate remaining msm8998 resetsJeffrey Hugo2018-12-051-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: Add xo dummy clk on msm8998Stephen Boyd2018-12-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have this dummy factor clk in place to workaround a missing rpm clk driver that can manage the XO clk state. Add it in to match what we do on msm8996. Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Marc Gonzalez <marc.w.gonzalez@free.fr> Tested-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | clk: qcom: Fix MSM8998 resetsJeffrey Hugo2018-12-031-19/+19
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | The offsets for the defined BCR reset registers does not match the hardware documentation. Update the values to match the hardware documentation. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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*-. \ \ Merge branches 'clk-managed-registration', 'clk-spdx', 'clk-remove-basic' ↵Stephen Boyd2018-12-141-4/+2
|\ \ \ \ | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-ops-const' into clk-next - Make devm_of_clk_add_hw_provider() use parent dt node if necessary - Various SPDX taggings - Mark clk_ops const when possible * clk-managed-registration: clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock clk: apcs-msm8916: simplify probe cleanup by using devm clk: clk-twl6040: Free of_provider at remove clk: rk808: use managed version of of_provider registration clk: clk-hi655x: Free of_provider at remove clk: of-provider: look at parent if registered device has no provider info clk: Add kerneldoc to managed of-provider interfaces * clk-spdx: clk: Tag basic clk types with SPDX clk: Tag clk core files with SPDX clk: bcm2835: Switch to SPDX identifier * clk-remove-basic: clk: Loongson1: Remove usage of CLK_IS_BASIC clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC clk: versatile: sp810: Remove usage of CLK_IS_BASIC clk: hisilicon: Remove usage of CLK_IS_BASIC clk: h8300: Remove usage of CLK_IS_BASIC clk: axm5516: Remove usage of CLK_IS_BASIC clk: st: Remove usage of CLK_IS_BASIC clk: renesas: Remove usage of CLK_IS_BASIC * clk-ops-const: clk: s2mps11: constify clk_ops structure clk: pxa: constify clk_ops structures clk: pistachio: constify clk_ops structures clk: palmas: constify clk_ops structure clk: max77686: constify clk_ops structure
| * | | clk: apcs-msm8916: simplify probe cleanup by using devmMatti Vaittinen2018-12-051-4/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | use devm variant for of_provider registration. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> [sboyd@kernel.org: Drop unused parent pointer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | | Merge branch 'clk-qcom-sdm845-lpass' into clk-nextStephen Boyd2018-12-144-0/+223
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Qualcomm SDM845 audio subsystem clks * clk-qcom-sdm845-lpass: clk: qcom: Add lpass clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM LPASS clock bindings dt-bindings: clock: Update GCC bindings for protected-clocks
| * | | clk: qcom: Add lpass clock controller driver for SDM845Taniya Das2018-12-034-0/+224
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. LPASS clocks present on the global clock controller would be registered with the clock framework based on the protected-clock flag. Also do not gate these clocks if they are left unused, as the lpass clocks require the global clock controller lpass clocks to be enabled before they are accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock access. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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*-------. \ \ Merge branches 'clk-qcom-kconfig', 'clk-qcom-gpucc', 'clk-qcom-qcs404-rpm', ↵Stephen Boyd2018-12-146-37/+324
|\ \ \ \ \ \ \ | | | | | |/ / | |_|_|_|_| / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-qcom-spi' and 'clk-qcom-videocc-binding' into clk-next - Qualcomm SDM845 GPU clock controllers - Qualcomm QCS404 RPM clk support * clk-qcom-kconfig: clk: qcom: Move to menuconfig and reduce lines * clk-qcom-gpucc: dt-bindings: clock: qcom: Fix the xo parent in gpucc example clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6 clk: qcom: Add a dummy enable function for GX gdsc clk: qcom: gdsc: Don't override existing gdsc pd functions clk: qcom: Add graphics clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Graphics clock bindings * clk-qcom-qcs404-rpm: clk: qcom: smd: Add support for QCS404 rpm clocks * clk-qcom-spi: clk: qcom: msm8916: Additional clock rates for spi * clk-qcom-videocc-binding: dt-bindings: clock: Require #reset-cells in sdm845-videocc
| | | | * | clk: qcom: msm8916: Additional clock rates for spiLoic Poulain2018-11-301-0/+4
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI friendly clock rates to the spi freq table. Today it's not possible to use SPI at lower than 960Khz. This patch adds 100/250/500/1000 kHz configs to the table. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * | clk: qcom: smd: Add support for QCS404 rpm clocksTaniya Das2018-11-061-0/+45
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add rpm smd clocks, PMIC and bus clocks which are required on QCS404 for clients to vote on. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> [bjorn: Dropped cxo, voter clocks and static initialization] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6Douglas Anderson2018-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an earlier version of commit 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") there were 6 listed parents for "gpu_cc_gmu_clk_src". In the version that landed there were 5. ...but "num_parents" was still left at 6. On my system this goes boom at bootup. Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: qcom: Add a dummy enable function for GX gdscJordan Crouse2018-11-271-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: qcom: gdsc: Don't override existing gdsc pd functionsJordan Crouse2018-11-271-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In extreme cases an individual gdsc may wish to override the power domain enable or disable callback functions for their own purposes. Only set the generic gdsc callback if the function pointers are not already set. Acked-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: qcom: Add graphics clock controller driver for SDM845Amit Nischal2018-11-273-0/+236
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the graphics clock controller found on SDM845 based devices. This would allow graphics drivers to probe and control their clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Collapse return in probe into less lines] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: qcom: Move to menuconfig and reduce linesStephen Boyd2018-12-101-35/+10
| |/ | | | | | | | | | | | | | | | | | | | | We duplicate the 'depends on' in almost every Kconfig here, and it's getting out of hand now that we have tens of options for various SoC drivers here. Let's clean it up a little by making a menuconfig for a submenu and adding an if wrapper around the driver section. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: Support 'protected-clocks' propertyStephen Boyd2018-11-211-0/+18
|/ | | | | | | | | | | | | | | | | | Certain firmware configurations "protect" clks and cause the entire system to reboot when a non-secure OS such as Linux tries to read or write protected clk registers. But other firmware configurations allow reading or writing the same registers, and they may actually require that the OS use the otherwise locked down clks. Support the 'protected-clocks' property by never registering these protected clks with the common clk framework. This way, when firmware is protecting these clks we won't have the chance to ever read or write these registers and take down the entire system. Cc: Taniya Das <tdas@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-fixed-rate-remove' and 'clk-qcom-cleanup' into clk-nextStephen Boyd2018-10-181-16/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | * clk-fixed-rate-remove: clk: fixed-rate: fix of_node_get-put imbalance * clk-qcom-cleanup: clk: qcom: Remove unused arrays in SDM845 GCC
| | * clk: qcom: Remove unused arrays in SDM845 GCCEvan Green2018-10-181-16/+0
| |/ | | | | | | | | | | | | | | This change removes a parent map and parent name array that appear to be completely unreferenced. Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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*-. \ Merge branches 'clk-imx6-mmdc', 'clk-qcom-krait', 'clk-rockchip' and ↵Stephen Boyd2018-10-1811-0/+1321
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-smp2s11-match' into clk-next - iMX6 MMDC clks - Qualcomm Krait CPU clk support * clk-imx6-mmdc: clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock clk: imx6ul: add mmdc1 ipg clock * clk-qcom-krait: clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions * clk-rockchip: clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call clk: rockchip: use the newly added clock-id for hdmi on RK3066 clk: rockchip: add clock-id for HCLK_HDMI on rk3066 clk: rockchip: fix wrong mmc sample phase shift for rk3328 clk: rockchip: improve rk3288 pll rates for better hdmi output * clk-smp2s11-match: clk: s2mps11: Add used attribute to s2mps11_dt_match clk: s2mps11: Fix matching when built as module and DT node contains compatible
| | * clk: qcom: Add safe switch hook for krait mux clocksSricharan R2018-10-173-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Hfplls are reprogrammed during the rate change, the primary muxes which are sourced from the same hfpll for higher frequencies, needs to be switched to the 'safe secondary mux' as the parent for that small window. This is done by registering a clk notifier for the muxes and switching to the safe parent in the PRE_RATE_CHANGE notifier and back to the original parent in the POST_RATE_CHANGE notifier. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add Krait clock controller driverStephen Boyd2018-10-174-2/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add KPSS ACC/GCC driverStephen Boyd2018-10-173-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add support for Krait clocksStephen Boyd2018-10-174-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15 registers. Support these clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> [sboyd@kernel.org: Move hidden config to top outside of the visible qcom config zone so that menuconfig looks nice] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add IPQ806X's HFPLLsStephen Boyd2018-10-171-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | Describe the HFPLLs present on IPQ806X devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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