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path: root/drivers/clk/socfpga
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* clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen2021-09-241-9/+0
* clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen2021-07-261-1/+1
* clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen2021-07-261-0/+9
* clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen2021-07-261-4/+4
* clk: socfpga: clk-pll: Remove unused variable 'rc'Jian Xin2021-06-271-2/+1
* clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen2021-06-271-3/+8
* clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen2021-06-273-2/+123
* clk: agilex/stratix10: fix bypass representationDinh Nguyen2021-06-272-21/+91
* clk: agilex/stratix10: remove noc_clkDinh Nguyen2021-06-272-34/+30
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2021-04-2812-180/+202
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| *-. Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' a...Stephen Boyd2021-04-2712-181/+203
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| | | * clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski2021-03-291-1/+1
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| | * clk: socfpga: remove redundant initialization of variable divColin Ian King2021-04-072-2/+2
| | * clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King2021-04-071-0/+1
| | * clk: socfpga: Fix code formattingStephen Boyd2021-03-301-1/+2
| | * clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen2021-03-306-147/+159
| | * clk: socfpga: arria10: convert to use clk_hwDinh Nguyen2021-03-303-15/+16
| | * clk: socfpga: use clk_hw_register for a5/c5Dinh Nguyen2021-03-303-15/+22
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* | clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski2021-04-091-1/+1
* | clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)Krzysztof Kozlowski2021-03-232-3/+7
* | clk: socfpga: allow compile testing of Stratix 10 / Agilex clocksKrzysztof Kozlowski2021-03-231-3/+12
* | arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGAKrzysztof Kozlowski2021-03-231-2/+2
* | clk: socfpga: build together Stratix 10, Agilex and N5X clock driversKrzysztof Kozlowski2021-03-232-7/+6
* | clk: socfpga: allow building N5X clocks with ARCH_N5XKrzysztof Kozlowski2021-03-232-2/+8
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*-. Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' into...Stephen Boyd2021-02-166-7/+240
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| | * clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'Lee Jones2021-02-111-2/+1
| | * clk: socfpga: clk-pll: Remove unused variable 'rc'Lee Jones2021-02-111-2/+1
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| * clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen2021-02-124-3/+238
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-10-221-13/+0
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| * clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing2020-09-221-13/+0
* | clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clkDinh Nguyen2020-09-221-1/+1
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* clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen2020-06-191-1/+1
* clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen2020-06-191-1/+5
* clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen2020-05-264-0/+526
* clk: socfpga: add const to _ops data structuresDinh Nguyen2020-05-263-4/+4
* clk: socfpga: remove clk_ops enable/disable methodsDinh Nguyen2020-05-263-6/+0
* clk: socfpga: stratix10: use new parent data schemeDinh Nguyen2020-05-265-41/+146
* clk: socfpga: stratix10: simplify parameter passingDinh Nguyen2020-02-125-92/+57
* clk: stratix10: use do_div() for 64-bit calculationDinh Nguyen2020-02-121-1/+3
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-09-202-14/+17
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| * clk: socfpga: deindent code to proper indentationStephen Boyd2019-08-161-2/+2
| * clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd2019-08-162-13/+16
* | clk: socfpga: stratix10: fix rate caclulationg for cnt_clksDinh Nguyen2019-08-141-1/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-1/+5
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| * clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen2019-06-251-2/+2
| * clk: socfpga: stratix10: add additional clocks needed for the NAND IPDinh Nguyen2019-06-251-1/+5
* | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2019-06-281-2/+2
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| * | clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen2019-06-251-2/+2
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* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner2019-06-051-10/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-303-36/+3
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