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* clk: sprd: add RTC gate for SC9860Chunyan Zhang2018-03-161-0/+76
| | | | | | | | | | | Add a few gate clocks which are used for gating RTC for some devices on AON area of SC9860. This patch has been tested on SC9860, with this patch and proper DT configurations, the watchdog can be initialized and work well. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-divider-container' into clk-nextStephen Boyd2018-01-261-1/+2
| | | | | | | * clk-divider-container: clk: divider: fix incorrect usage of container_of Plus fixup sprd/div.c to pass the width too.
* clk: sprd: add clocks support for SC9860Chunyan Zhang2017-12-213-0/+1987
| | | | | | | | This patch added the list of clocks for Spreadtrum's SC9860 SoC, together with clock initialization code. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sprd: add adjustable pll supportChunyan Zhang2017-12-213-0/+375
| | | | | | | Introduced a common adjustable pll clock driver for Spreadtrum SoCs. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sprd: add composite clock supportChunyan Zhang2017-12-213-0/+112
| | | | | | | | | This patch introduced composite driver for Spreadtrum's SoCs. The functions of this composite clock simply consist of divider and mux clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sprd: add divider clock supportChunyan Zhang2017-12-213-0/+166
| | | | | | | | This is a feature that can also be found in sprd composite clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sprd: add mux clock supportChunyan Zhang2017-12-213-0/+151
| | | | | | | | | This patch adds clock multiplexor support for Spreadtrum platforms, the mux clocks also can be found in sprd composite clocks, so provides two helpers that can be reused later on. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sprd: add gate clock supportChunyan Zhang2017-12-213-0/+171
| | | | | | | | Some clocks on the Spreadtrum's SoCs are just simple gates. Add support for those clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sprd: Add common infrastructureChunyan Zhang2017-12-214-0/+141
Added Spreadtrum's clock driver framework together with common structures and interface functions. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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