delta/linux.git - git.kernel.org: pub/scm/linux/kernel/git/torvalds/linux.git

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: tegra: Fix Tegra210 PLLU initialization	Alex Frid	2017-08-23	1	-2/+4
*	clk: tegra: Correct Tegra210 UTMIPLL poweron delay	Alex Frid	2017-08-23	1	-3/+3
*	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	2017-08-23	1	-1/+1
*	clk: tegra: don't warn for pll_d2 defaults unnecessarily	Peter De Schrijver	2017-08-23	1	-2/+4
*	clk: tegra: Fix T210 effective NDIV calculation	Alex Frid	2017-08-23	1	-4/+5
*	clk: tegra210: remove non-existing VFIR clock	Peter De Schrijver	2017-08-23	1	-1/+0
*	clk: tegra: disable SSC for PLL_D2	Peter De Schrijver	2017-08-23	1	-1/+1
*	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter	2017-04-04	1	-4/+4
*	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	2017-04-04	1	-0/+7
*	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver	2017-03-20	1	-0/+2
*	clk: tegra: Add SATA seq input control	Peter De Schrijver	2017-03-20	1	-0/+25
*	clk: tegra: Add Tegra210 special resets	Peter De Schrijver	2017-03-20	1	-0/+85
*	clk: tegra: Rework pll_u	Peter De Schrijver	2017-03-20	1	-23/+272
*	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver	2017-03-20	1	-0/+26
*	clk: tegra: Add aclk	Peter De Schrijver	2017-03-20	1	-0/+10
*	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver	2017-03-20	1	-0/+3
*	clk: tegra: Define Tegra210 DMIC sync clocks	Peter De Schrijver	2017-03-20	1	-0/+6
*	clk: tegra: Add CEC clock	Peter De Schrijver	2017-03-20	1	-0/+1
*	clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation	Peter De Schrijver	2017-03-20	1	-1/+7
*	clk: tegra: Don't warn for PLL defaults unnecessarily	Peter De Schrijver	2017-03-20	1	-6/+12
*	clk: tegra: Remove non-existing pll_m_out1 clock	Peter De Schrijver	2017-03-20	1	-5/+0
*	clk: tegra: Fix ISP clock modelling	Peter De Schrijver	2017-03-20	1	-0/+1
*	clk: tegra: Fix pll_a1 iddq register, add pll_a1	Peter De Schrijver	2017-03-20	1	-1/+2
*	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	2016-06-30	1	-179/+3
*	clk: tegra: Micro-optimize Tegra210 clock setup	Thierry Reding	2016-06-23	1	-4/+4
*	clk: tegra: Make sor_safe the parent of dpaux and dpaux1	Thierry Reding	2016-06-23	1	-2/+2
*	clk: tegra: Enable sor1 and sor1_src on Tegra210	Thierry Reding	2016-06-17	1	-0/+2
*	clk: tegra: Disable spread spectrum on pll_d2	Thierry Reding	2016-06-17	1	-2/+3
*	clk: tegra: Fixup post dividers on Tegra210	Thierry Reding	2016-06-10	1	-47/+47
*	remove lots of IS_ERR_VALUE abuses	Arnd Bergmann	2016-05-27	1	-1/+1
*	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	2016-04-28	1	-2/+14
*	clk: tegra: Add sor_safe clock	Thierry Reding	2016-04-28	1	-0/+4
*	clk: tegra: dpaux and dpaux1 are fixed factor clocks	Thierry Reding	2016-04-28	1	-0/+8
*	clk: tegra: Add dpaux1 clock	Thierry Reding	2016-04-28	1	-0/+1
*	clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs	Andrew Bresticker	2016-04-28	1	-0/+58
*	clk: tegra: Fix sparse warnings for functions not declared as static	Jon Hunter	2016-02-02	1	-17/+19
*	clk: tegra: Fix sparse warning for pll_m	Jon Hunter	2016-02-02	1	-1/+1
*	clk: tegra: Use definition for pll_u override bit	Jon Hunter	2016-02-02	1	-1/+1
*	clk: tegra: Fix warning caused by pll_u failing to lock	Jon Hunter	2016-02-02	1	-2/+0
*	clk: tegra: Fix clock sources for Tegra210 EMC	Jon Hunter	2016-02-02	1	-1/+2
*	clk: tegra: Add the APB2APE audio clock on Tegra210	Jon Hunter	2016-02-02	1	-0/+1
*	clk: tegra: Fix pllx dyn step calculation	Rhyland Klein	2016-02-02	1	-5/+5
*	clk: tegra: Fix naming of MISC registers	Rhyland Klein	2016-02-02	1	-18/+18
*	clk: tegra: Remove improper flags for lock_enable	Rhyland Klein	2016-01-25	1	-28/+14
*	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein	2015-12-17	1	-0/+2852