summaryrefslogtreecommitdiff
path: root/drivers/crypto/chelsio/chcr_crypto.h
Commit message (Collapse)AuthorAgeFilesLines
* crypto: chelsio - Swap location of AAD and IV sent in WRHarsh Jain2018-12-231-7/+3
| | | | | | | | Send input as IV | AAD | Data. It will allow sending IV as Immediate Data and Creates space in Work request to add more dma mapped entries. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Herbert Xu2018-10-171-0/+2
|\ | | | | | | Merge crypto tree to pick up chelsio bug fix.
| * crypto: chelsio - Fix memory corruption in DMA Mapped buffers.Harsh Jain2018-09-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Update PCI Id in "cpl_rx_phys_dsgl" header. In case pci_chan_id and tx_chan_id are not derived from same queue, H/W can send request completion indication before completing DMA Transfer. Herbert, It would be good if fix can be merge to stable tree. For 4.14 kernel, It requires some update to avoid mege conficts. Cc: <stable@vger.kernel.org> Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | crypto: chelsio - Remove VLA usage of skcipherKees Cook2018-09-281-1/+1
|/ | | | | | | | | | | | | In the quest to remove all stack VLA usage from the kernel[1], this replaces struct crypto_skcipher and SKCIPHER_REQUEST_ON_STACK() usage with struct crypto_sync_skcipher and SYNC_SKCIPHER_REQUEST_ON_STACK(), which uses a fixed stack size. [1] https://lkml.kernel.org/r/CA+55aFzCG-zNmZwX4A2FQpadafLfEzK6CC=qPXydAacU1RqZWA@mail.gmail.com Cc: Harsh Jain <harsh@chelsio.com> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio - Remove separate buffer used for DMA map B0 block in CCMHarsh Jain2018-05-311-6/+6
| | | | | | | | Extends memory required for IV to include B0 Block and DMA map in single operation. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypt: chelsio - Send IV as Immediate for cipher algoHarsh Jain2018-05-311-2/+1
| | | | | | | Send IV in WR as immediate instead of dma mapped entry for cipher. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio - Remove declaration of static function from headerHarsh Jain2018-03-311-1/+0
| | | | | | | | | It fixes compilation warning introduced in commit Fixes: 5110e65536f3 ("crypto: chelsio - Split Hash requests for...") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio -Split Hash requests for large scatter gather listHarsh Jain2018-03-161-10/+22
| | | | | | | | Send multiple WRs to H/W when No. of entries received in scatter list cannot be sent in single request. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio - Add authenc versions of ctr and shaHarsh Jain2018-01-181-2/+5
| | | | | | | Add ctr and sha combination of algo in authenc mode. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* chcr: Add support for Inline IPSecAtul Gupta2017-11-291-45/+24
| | | | | | | | | | | | register xfrmdev_ops callbacks, Send IPsec tunneled data to HW for inline processing. The driver use hardware crypto accelerator to encrypt and generate ICV for the transmitted packet in Inline mode. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio - Move DMA un/mapping to chcr from lld cxgb4 driverHarsh Jain2017-11-031-29/+85
| | | | | | | | | Allow chcr to do DMA mapping/Unmapping instead of lld cxgb4. It moves "Copy AAD to dst buffer" requirement from driver to firmware. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio - Remove allocation of sg list to implement 2K limit of dsgl ↵Harsh Jain2017-11-031-6/+0
| | | | | | | | | header Update DMA address index instead of allocating new sg list to impose 2k size limit for each entry. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chelsio - Use x8_ble gf multiplication to calculate IV.Harsh Jain2017-11-031-0/+1
| | | | | | | gf128mul_x8_ble() will reduce gf Multiplication iteration by 8. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Avoid algo allocation in softirq.Harsh Jain2017-07-121-0/+1
| | | | | | | | Thsi patch fixes calling "crypto_alloc_cipher" call in bottom halves. Pre allocate aes cipher required to update Tweak value for XTS. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Ensure Destination sg entry size less than 2kHarsh Jain2017-06-201-0/+6
| | | | | | | | Allocate new sg list in case received destination sg list has entry greater that 2k. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Add ctr mode and process large sg entries for cipherHarsh Jain2017-06-201-3/+16
| | | | | | | | It send multiple WRs to H/W to handle large sg lists. Adds ctr(aes) and rfc(ctr(aes)) modes. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Add fallback for AEAD algosHarsh Jain2017-04-211-1/+2
| | | | | | | | | | Fallback to sw when I AAD length greater than 511 II Zero length payload II No of sg entries exceeds Request size. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Fix txq ids.Harsh Jain2017-04-211-1/+2
| | | | | | | | | | | The patch fixes a critical issue to map txqid with flows on the hardware appropriately, if tx queues created are more than flows configured then txqid shall map within the range of hardware flows configured. This ensure that un-mapped txqid does not remain un-handled. The patch also segregated the rxqid and txqid for clarity. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Reviewed-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Increase priority of AEAD algos.Harsh Jain2017-04-211-2/+2
| | | | | | | | | | | templates(gcm,ccm etc) inherit priority value of driver to calculate its priority. In some cases template priority becomes more than driver priority for same algo. Without this patch we will not be able to use driver authenc algos. It will be good if it pushed in stable kernel. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Change algo priorityHarsh Jain2017-02-031-1/+1
| | | | | | | Update priorities to 3000 Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Fix panic on dma_unmap_sgHarsh Jain2017-02-031-0/+3
| | | | | | | Save DMA mapped sg list addresses to request context buffer. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Add AEAD algos.Harsh Jain2016-11-301-7/+83
| | | | | | | | | Add support for following AEAD algos. GCM,CCM,RFC4106,RFC4309,authenc(hmac(shaXXX),cbc(aes)). Reviewed-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Move tfm ctx variable to request contextHarsh Jain2016-11-301-5/+4
| | | | | | | Move request specific data in request context. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Use SHASH_DESC_ON_STACKHarsh Jain2016-11-301-1/+1
| | | | | | | | Use SHASH_DESC_ON_STACK macro to allocate memory for ipad/opad calculation. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Calculate Reverse round key in setkey callback.Harsh Jain2016-11-301-1/+1
| | | | | | | Move reverse round key calculation logic in setkey operation. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Remove dynamic allocationHarsh Jain2016-11-301-3/+5
| | | | | | | | Remove malloc/free in hash operation and allocate memory in chcr_ahash_req_ctx structure. Signed-off-by: Jitendra Lulla <JLULLA@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: chcr - Added new structure chcr_wrHarsh Jain2016-11-301-6/+0
| | | | | | | Added new structure chcr_wr to populate Work Request Header. Signed-off-by: Jitendra Lulla <JLULLA@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* chcr: Support for Chelsio's Crypto HardwareHariprasad Shenai2016-08-181-0/+203
The Chelsio's Crypto Hardware can perform the following operations: SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224), HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC, AES-256-CBC, AES-128-XTS, AES-256-XTS This patch implements the driver for above mentioned features. This driver is an Upper Layer Driver which is attached to Chelsio's LLD (cxgb4) and uses the queue allocated by the LLD for sending the crypto requests to the Hardware and receiving the responses from it. The crypto operations can be performed by Chelsio's hardware from the userspace applications and/or from within the kernel space using the kernel's crypto API. The above mentioned crypto features have been tested using kernel's tests mentioned in testmgr.h. They also have been tested from user space using libkcapi and Openssl. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
View Lorry Controller Status