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* edac: Remove the legacy EDAC ABIMauro Carvalho Chehab2012-05-281-1/+1
| | | | | | | | Now that all drivers got converted to use the new ABI, we can drop the old one. Acked-by: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* amd64_edac: convert driver to use the new edac ABIMauro Carvalho Chehab2012-05-281-45/+92
| | | | | | | | | The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* edac: move nr_pages to dimm structMauro Carvalho Chehab2012-05-281-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of pages is a dimm property. Move it to the dimm struct. After this change, it is possible to add sysfs nodes for the DIMM's that will properly represent the DIMM stick properties, including its size. A TODO fix here is to properly represent dual-rank/quad-rank DIMMs when the memory controller represents the memory via chip select rows. Reviewed-by: Aristeu Rozanski <arozansk@redhat.com> Acked-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* edac: Don't initialize csrow's first_page & friends when not neededMauro Carvalho Chehab2012-05-281-35/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all edac drivers initialize csrow_info->first_page, csrow_info->last_page and csrow_info->page_mask. Those vars are used inside the EDAC core, in order to calculate the csrow affected by an error, by using the routine edac_mc_find_csrow_by_page(). However, very few drivers actually use it: e752x_edac.c e7xxx_edac.c i3000_edac.c i82443bxgx_edac.c i82860_edac.c i82875p_edac.c i82975x_edac.c r82600_edac.c There also a few other drivers that have their own calculus formula internally using those vars. All the others are just wasting time by initializing those data. While initializing data without using them won't cause any troubles, as those information is stored at the wrong place (at csrows structure), it is better to remove what is unused, in order to simplify the next patch. Reviewed-by: Aristeu Rozanski <arozansk@redhat.com> Acked-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Jiri Kosina <jkosina@suse.cz> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* edac: move dimm properties to struct dimm_infoMauro Carvalho Chehab2012-05-281-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On systems based on chip select rows, all channels need to use memories with the same properties, otherwise the memories on channels A and B won't be recognized. However, such assumption is not true for all types of memory controllers. Controllers for FB-DIMM's don't have such requirements. Also, modern Intel controllers seem to be capable of handling such differences. So, we need to get rid of storing the DIMM information into a per-csrow data, storing it, instead at the right place. The first step is to move grain, mtype, dtype and edac_mode to the per-dimm struct. Reviewed-by: Aristeu Rozanski <arozansk@redhat.com> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: James Bottomley <James.Bottomley@parallels.com> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Mike Williams <mike@mikebwilliams.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* EDAC: Make pci_device_id tables __devinitconst.Lionel Debroux2012-03-191-1/+1
| | | | | | | | | | | | | | | These const tables are currently marked __devinitdata, but Documentation/PCI/pci.txt says: "o The ID table array should be marked __devinitconst; this is done automatically if the table is declared with DEFINE_PCI_DEVICE_TABLE()." So use DEFINE_PCI_DEVICE_TABLE(x). Based on PaX and earlier work by Andi Kleen. Signed-off-by: Lionel Debroux <lionel_debroux@yahoo.fr> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix K8 revD and later chip select sizesBorislav Petkov2012-03-191-4/+28
| | | | | | | | Fix DRAM chip select sizes calculation for K8, revisions D and E. Reported-by: Niklas Söderlund <niklas.soderlund@ericsson.com Link: http://lkml.kernel.org/r/1320849178-23340-1-git-send-email-niklas.soderlund@ericsson.com Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix missing csrows sysfs nodesAshish Shenoy2012-03-191-9/+7
| | | | | | | | | | | | | | | | | While initializing the array of csrow attribute instances, a few csrows were uninitialized. This happened because the module only performed a check for DRAM base ctl register0's and not DRAM base ctl register1's chip select enable bit. There could be systems with DIMMs populated on only single memory channel whereas the module also assumed that a dual channel dimm had double the memory size of a single memory channel instead of checking the memory on each channel. This patch fixes these above issues. Signed-off-by: Ashish Shenoy <ashenoy@riverbed.com> Signed-off-by: Prasanna S. Panchamukhi <ppanchamukhi@riverbed.com> Link: http://lkml.kernel.org/r/4F459CFA.5090604@riverbed.com Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup return type of amd64_determine_edac_cap()Dan Carpenter2011-10-061-2/+2
| | | | | | | | | | Sparse complains that edac_cap was declared as dev_type and we are returning edac_type. Historically, edac_type was correct but since then we have changed it to return a bit field. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: http://lkml.kernel.org/r/20111006063025.GA2615@mwanda Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Add a fix for Erratum 505Borislav Petkov2011-10-061-5/+22
| | | | | | | | | When accessing the scrub rate control register (F3x58) on F15h, the DRAM controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the scrub rate configuration can take effect. See Erratum 505 in the AMD F15h revision guide for more details. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC, MCE, AMD: Simplify NB MCE decoder interfaceBorislav Petkov2011-10-061-4/+2
| | | | | | | | Drop third nbcfg argument which is old remains and not required anymore. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Erratum #637 workaroundBorislav Petkov2011-04-261-2/+50
| | | | | | | | | F15h CPUs may report a non-DRAM address when reporting an error address belonging to a CC6 state save area. Add a workaround to detect this condition and compute the actual DRAM address of the error as documented in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Factor in CC6 save areaBorislav Petkov2011-04-261-1/+27
| | | | | | | | | | F15h and later use a portion of DRAM as a CC6 storage area. BIOS programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by subtracting the storage area from the DRAM limit setting. However, in order for edac to consider that part of DRAM too, we need to include it into the per-node range. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Remove node interleave warningBorislav Petkov2011-04-261-5/+1
| | | | | | | | | This warning was wrongfully added for a normal condition - intlvsel actually selects the destination node when node interleaving is enabled and it is not a mismatch. For a detailed example, see section 2.8.10.2 "Node Interleaving" in F10h BKDG. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* EDAC: Remove debugging output in scrub rate handlingMarkus Trippelsdorf2011-04-211-2/+0
| | | | | | | | | This patch removes superfluous debugging output in the sysfs scrub rate handler. It also consolidates the error handling in the scrub rate accessors. Signed-off-by: Markus Trippelsdorf <markus@trippelsdorf.de> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix potential memleakBorislav Petkov2011-03-291-1/+1
| | | | | | | | | | We check the pointers together but at least one of them could be invalid due to failed allocation. Since we cannot continue if either of the two allocations has failed, exit early by freeing them both. Cc: <stable@kernel.org> # 38.x Reported-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix decode_syndrome typesBorislav Petkov2011-03-171-4/+4
| | | | | | Those should all be unsigned. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix DCT argument typeBorislav Petkov2011-03-171-5/+4
| | | | | | | | Fix amd64_debug_display_dimm_sizes() arguments order per convention (pvt is always first). Also, the now second arg denotes the DCT so adjust its type. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix ranges signednessBorislav Petkov2011-03-171-4/+5
| | | | | | The dram ranges make sense only as an unsigned type. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Drop local variableBorislav Petkov2011-03-171-3/+2
| | | | | | Use the macro directly instead Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix PCI config addressing typesBorislav Petkov2011-03-171-5/+5
| | | | | | Adjust argument types to the PCI config API's types. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix DRAM base macrosBorislav Petkov2011-03-171-2/+1
| | | | | | Return unsigned u8 values only. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix node id signednessBorislav Petkov2011-03-171-7/+9
| | | | | | | | A node id can never be negative since we use it as an index into the DRAM ranges array. This also makes one of the BUG_ON conditions redundant. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Enable driver on F15hBorislav Petkov2011-03-171-7/+23
| | | | | | | | | Add the PCI device ids required for driver registration. Remove pvt->ctl_name and use the family descriptor directly, instead. Then, bump driver version and fixup its format. Finally, enable DRAM ECC decoding on F15h. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Adjust ECC symbol size to F15hBorislav Petkov2011-03-171-17/+15
| | | | | | | F15h has the same ECC symbol size options as F10h revD and later so adjust checks to that. Simplify code a bit. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Simplify scrubrate settingBorislav Petkov2011-03-171-3/+5
| | | | | | Drop per-instance variable and compute min scrubrate dynamically. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Improve DRAM address mappingBorislav Petkov2011-03-171-68/+81
| | | | | | | | Drop static tables which map the bits in F2x80 to a chip select size in favor of functions doing the mapping with some bit fiddling. Also, add F15 support. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Sanitize ->read_dram_ctl_registerBorislav Petkov2011-03-171-7/+7
| | | | | | | This function is relevant for F10h and higher, and it has only one callsite so drop its function pointer from the low_ops struct. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Adjust sys_addr to chip select conversion routine to F15hBorislav Petkov2011-03-171-14/+15
| | | | | | | F15h sys_addr to chip select mapping is almost identical to F10h's so reuse that. Rename functions on that path accordingly. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Beef up early exit reportingBorislav Petkov2011-03-171-1/+12
| | | | | | | Add paranoid checks for the sys address before going off and decoding it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Revamp online spare handlingBorislav Petkov2011-03-171-17/+13
| | | | | | | Replace per-DCT macros with smarter ones, drop hack and look for the spare rank on all chip selects on a channel. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Fix channel interleave removalBorislav Petkov2011-03-171-9/+17
| | | | | | | Remove the channel interleave select bit properly. See F2x110[DctSelIntLvAddr] for details. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Correct node interleaving removalBorislav Petkov2011-03-171-4/+4
| | | | | | | | | When node interleaving is enabled, a subset of the addr[14:12] bits has to be removed in order to get the normalized DCT address of the DRAM channel. The actual number of bits to remove is determined by F1x[1, 0][7C:40][IntlvEn]. Do this correctly. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Add support for interleaved region swappingBorislav Petkov2011-03-171-0/+38
| | | | | | | | | On revC3 and revE Fam10h machines and later, non-interleaved graphics framebuffer memory under the 16G mark can be swapped with a region located at the bottom of memory so that the GPU can use the interleaved region and thus two channels. Add support for that. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Unify get_error_addressBorislav Petkov2011-03-171-13/+13
| | | | | | | | | The address bits from MC4_STATUS differ only between K8 and the rest so no need for a per-family method. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Simplify decoding pathBorislav Petkov2011-03-171-49/+27
| | | | | | | | | Use the struct mce directly instead of copying from it into a custom struct err_regs. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Adjust channel counting to F15hBorislav Petkov2011-03-171-7/+6
| | | | | | | The only difference is that F10h used to sport ganged DCTs and F15h doesn't so adjust the F10h routine and reuse it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup old defines cruftBorislav Petkov2011-03-171-13/+13
| | | | | | Remove unused defines, drop family names from define names. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup NBSH cruftBorislav Petkov2011-03-171-13/+2
| | | | | | | | | Remove reporting of errors with UC bit set - this is done by the MCE decoding code anyway and this driver deals with DRAM ECC errors only. UC (NB uncorrectable error) doesn't necessarily mean it is a DRAM error. Remove unused macros while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup NBCFG handlingBorislav Petkov2011-03-171-24/+21
| | | | | | | | | The fact whether we are chipkill capable or not does not have any bearing when computing the channel index on a ganged DCT configuration so remove that. Also, simplify debug statements. Finally, remove old error injection leftovers, while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup NBCTL codeBorislav Petkov2011-03-171-7/+7
| | | | | | | | | Remove family names from macro names, drop single bit defines and comment their meaning instead. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup DCT Select Low/High codeBorislav Petkov2011-03-171-10/+10
| | | | | | | | | Shorten macro names, remove family name from macros, fix macro arguments, shorten debug strings. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup Dram Configuration registers handlingBorislav Petkov2011-03-171-25/+17
| | | | | | | | | | | | | * Restrict DCT ganged mode check since only Fam10h supports it * Adjust DRAM type detection for BD since it only supports DDR3 * Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do that in read_mc_regs() * Cleanup comments and remove family names from register macros * Remove unused defines There should be no functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup DBAM handlingBorislav Petkov2011-03-171-19/+8
| | | | | | | | Do not read DBAM regs twice and simplify code around them. There should be no functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Replace huge bitmasks with a macroBorislav Petkov2011-03-171-10/+9
| | | | | | Replace hard to read hex constants with a continuous masks macro. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Sanitize f10_get_base_addr_offsetBorislav Petkov2011-03-171-38/+45
| | | | | | | | | | | | This function maps the system address to the normalized DCT address. Document what the code does for more clarity and wrap insane bitmasks in a more understandable macro which generates them. Also, reduce number of arguments passed to the function. Finally, rename this function to what it actually does. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Sanitize channel extractionBorislav Petkov2011-03-171-50/+34
| | | | | | | | | | Cleanup and simplify f10_determine_channel(); make it more readable. Also drop f10_map_intlv_en_to_shift() in favor of simply counting the bits in F1x124[DramIntlvEn] which is equivalent. There should be no functionality change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup chipselect handlingBorislav Petkov2011-03-171-182/+111
| | | | | | | | | | | | Add a struct representing the DRAM chip select base/limit register pairs. Concentrate all CS handling in a single function. Also, add CS looping macros for cleaner, more readable code. While at it, adjust code to F15h. Finally, do smaller macro names cleanups (remove family names from register macros) and debug messages clarification. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Cleanup DHAR handlingBorislav Petkov2011-03-171-18/+18
| | | | | | Adjust to F15h, simplify code, fixup macros. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* amd64_edac: Remove DRAM base/limit subfields cachingBorislav Petkov2011-03-171-166/+64
| | | | | | | | | | | | | | | | | Add a struct representing the DRAM base/limit range pairs and remove all cached subfields. Replace them with accessor functions, which actually saves us some space: text data bss dec hex filename 14712 1577 336 16625 40f1 drivers/edac/amd64_edac_mod.o.after 14831 1609 336 16776 4188 drivers/edac/amd64_edac_mod.o.before Also, it simplifies the code a lot allowing to merge the K8 and F10h routines. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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