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path: root/drivers/gpu/drm/nouveau/nvc0_fence.c
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* drm/nouveau: remove as much direct use of core headers as possibleBen Skeggs2014-08-101-4/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port to nvif client/device/objectsBen Skeggs2014-08-101-2/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv84-/fence: prepare for emit/sync support of sysram sequencesBen Skeggs2013-02-201-30/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: make internal hooks part of the contextBen Skeggs2013-02-201-6/+13
| | | | | | | A step towards being able to provide fences from other engines not connected to PFIFO. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv84-/fence: abstract class emit/sync functions to virt+sequenceBen Skeggs2013-02-201-26/+14
| | | | | | | Now can be used to operate on any buffer mapped into the GPU virtual address and not just the main inter-channel sync buffer. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv84/fence: access fences with full virtual address, not offsetBen Skeggs2013-02-201-128/+10
| | | | | | | | Allows most of the code to be shared between nv84/nvc0 implementations, and paves the way for doing emit/sync on non-VRAM buffers (multi-gpu, dma-buf). Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence/nv84-: put processes to sleep while waiting on fencesBen Skeggs2013-02-201-2/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: unpin various bo's before destroyingMarcin Slusarz2012-11-291-1/+6
| | | | | | | These objects leak VRAM - but only on module unload. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: rename nvd0_display to nv50_display to reflect reality since mergeBen Skeggs2012-11-291-2/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-nvc0: switch to common disp impl, removing previous versionBen Skeggs2012-11-291-17/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port remainder of drm code, and rip out compat layerBen Skeggs2012-10-031-4/+6
| | | | | | | | v2: Ben Skeggs <bskeggs@redhat.com> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port all engines to new engine module formatBen Skeggs2012-10-031-53/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pageflip: kick flip handling out of engsw and into fenceBen Skeggs2012-10-031-3/+40
| | | | | | | | | | This is all very much a policy thing, and hence will not belong in SW after the rework. engsw now only handles receiving the event to say "can flip now" and makes a callback to perform the actual work. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: un-port from nouveau_exec_engine interfacesBen Skeggs2012-10-031-35/+35
| | | | | | | | Still the same code, but not an "engine" anymore. The fence code is more of a policy decision rather than exposing mechanisms, so it's not appropriate to port it to the new engine subsystem. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: restructure source tree, split core from drm implementationBen Skeggs2012-10-031-2/+2
| | | | | | | | | | | | | | Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0/fence: restore pre-suspend fence buffer context on resumeBen Skeggs2012-10-031-0/+25
| | | | | | | | | Fixes some unfortunate races on resume. The G84 version of the code doesn't need this as "gpuobj"s are automagically suspended/resumed by the core code whereas pinned buffer objects are not. Cc: stable@vger.kernel.org Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: turn all fifo modules into engine modulesBen Skeggs2012-05-241-1/+2
| | | | | | | | | | | | | Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: fix a race where fence->channel can disappearBen Skeggs2012-05-241-2/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fence: convert to exec engine, and improve channel syncBen Skeggs2012-05-241-0/+182
Now have a somewhat simpler semaphore sync implementation for nv17:nv84, and a switched to using semaphores as fences on nv84+ and making use of the hardware's >= acquire operation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>