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path: root/drivers/gpu/drm/radeon/cik.c
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* drm/radeon/ci: make sure mc ucode is loaded before checking the sizeAlex Deucher2014-04-171-1/+3
| | | | | | | | Avoid a possible segfault. Noticed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: add support for newer mc ucode on CI (v2)Alex Deucher2014-04-171-9/+17
| | | | | | | | | | | | Fixes mclk stability on certain asics. v2: print out mc firmware version used and size bug: https://bugs.freedesktop.org/show_bug.cgi?id=75992 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: fix typo in spectre_golden_registersAlex Deucher2014-04-031-1/+1
| | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: fix endian swap on hawaii clear state buffer setupAlex Deucher2014-04-031-2/+2
| | | | | | | | Need to swap on BE. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: set PIPE_CONFIG for 1D and linear tiling modes on CIKMarek Olšák2014-03-251-3/+24
| | | | | | | | | | | | | | This fixes fast color clear with 1D-tiled single-sample surfaces and Hyper-Z corruption with 1D-tiled depth surfaces. Even though it seems it is not needed for 1D tiling, CMASK and HTILE are always 2D-tiled, thus the hw needs to know the actual pipe configuration for CMASK and HTILE addressing no matter what the tiling mode of the surface is. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
* Merge tag 'v3.14-rc7' into drm-nextDave Airlie2014-03-181-3/+7
|\ | | | | | | | | | | Linux 3.14-rc7 Backmerge to help out Intel guys.
| * drm/radeon/cik: properly set compute ring status on disableAlex Deucher2014-03-121-1/+4
| | | | | | | | | | | | | | | | | | When we disable the rings, set the status properly. If not other code pathes may try and use the rings which are not functional at this point. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon/cik: fix typo in documentationAlex Deucher2014-03-061-1/+1
| | | | | | | | | | | | Copy-paste typo. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: resume old pm lateAlex Deucher2014-03-061-1/+2
| | | | | | | | | | | | | | | | Moving the pm resume up in the init order to fix dpm seems to have regressed somes cases with the old pm code. Move it back to late resume. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: drop radeon_ring_force_activityChristian König2014-02-181-2/+0
| | | | | | | | | | | | | | | | | | The reason for the false positives was fixed quite some time ago and since most engines can still execute NOPs while being locked up it leads to false negatives. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: drop drivers copy of the rptrChristian König2014-02-181-5/+2
| | | | | | | | | | | | | | In all cases where it really matters we are using the read functions anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon/cik: enable/disable vce cg when encoding v2Alex Deucher2014-02-181-0/+5
| | | | | | | | | | | | | | | | | | | | Some of the vce clocks are automatic, others need to be manually enabled. For ease, just disable cg when vce is active. v2: rebased Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: fill in set_vce_clocks for CIK asicsAlex Deucher2014-02-181-0/+35
| | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: initial VCE support v4Christian König2014-02-181-0/+60
|/ | | | | | | | | | | Only VCE 2.0 support so far. v2: squashing multiple patches into this one v3: add IRQ support for CIK, major cleanups, basic code documentation v4: remove HAINAN from chipset list Signed-off-by: Christian König <christian.koenig@amd.com>
* drm/radeon: clean up active vram sizingAlex Deucher2014-01-291-0/+6
| | | | | | | | | | | | | If we are not able to properly initialize one of the gpu engines for buffer paging, we limit vram to the size of the cpu visible aperture. We generally either use the gfx or dma engine to do this. Clean up the size limiting code to only adjust the size based on what ring is selected for buffer paging rather than making assumptions about which engine is selected for paging. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* drm/radeon/cik: use hw defaults for TC_CFG registersAlex Deucher2014-01-201-14/+0
| | | | | | Use the hw power up values rather than 0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: use WAIT_REG_MEM special op for CP HDP flushAlex Deucher2014-01-201-9/+30
| | | | | | | | | This is the preferred flushing method on CIK. Note, this only works on the PFP so the engine bit must be set. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: consolidate cp hdp flushing code for CIKAlex Deucher2014-01-201-28/+27
| | | | | | | It's used in several places so move to a common shared function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "drm/radeon: disable CIK CP semaphores for now"Alex Deucher2014-01-201-5/+0
| | | | | | | This reverts commit 99b4f25122f43210278cde17a9d100906235a074. Semaphores work fine after further review and testing. Cc: 3.13 <stable@vger.kernel.org> # 3.13
* Merge branch 'drm-intel-next' of ↵Dave Airlie2014-01-201-5/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~danvet/drm-intel into drm-next drm-intel-next-2014-01-10: - final bits for runtime D3 on Haswell from Paul (now enabled fully) - parse the backlight modulation freq information in the VBT from Jani (but not yet used) - more watermark improvements from Ville for ilk-ivb and bdw - bugfixes for fastboot from Jesse - watermark fix for i830M (but not yet everything) - vlv vga hotplug w/a (Imre) - piles of other small improvements, cleanups and fixes all over Note that the pull request includes a backmerge of the last drm-fixes pulled into Linus' tree - things where getting a bit too messy. So the shortlog also contains a bunch of patches from Linus tree. Please yell if you want me to frob it for you a bit. * 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel: (609 commits) drm/i915/bdw: make sure south port interrupts are enabled properly v2 drm/i915: Include more information in disabled hotplug interrupt warning drm/i915: Only complain about a rogue hotplug IRQ after disabling drm/i915: Only WARN about a stuck hotplug irq ONCE drm/i915: s/hotplugt_status_gen4/hotplug_status_g4x/
| * drm/radeon: expose render backend mask to the userspaceMarek Olšák2013-12-231-0/+2
| | | | | | | | | | | | | | | | | | This will allow userspace to correctly program the PA_SC_RASTER_CONFIG register, so it can be considered a fix. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon: fix render backend setup for SI and CIKMarek Olšák2013-12-231-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the render backends of the first shader engine were enabled. The others were erroneously disabled. Enabling the other render backends improves performance a lot. Unigine Sanctuary on Bonaire: Before: 15 fps After: 90 fps Judging from the fan noise, the GPU was also underclocked when the other render backends were disabled, resulting in horrible performance. The fan is a lot noisy under load now. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | drm/radeon: implement pci config reset for CIK (v3)Alex Deucher2014-01-081-0/+161
| | | | | | | | | | | | | | | | | | | | | | pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: fix rebase v3: hide behind module parameter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: remove generic rptr/wptr functions (v2)Alex Deucher2013-12-241-17/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | Fill in asic family specific versions rather than using the generic version. This lets us handle asic specific differences more easily. In this case, we disable sw swapping of the rtpr writeback value on r6xx+ since the hw does it for us. Fixes bogus rptr readback on BE systems. v2: remove missed cpu_to_le32(), add comments Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon/pm: move pm handling into the asic specific codeAlex Deucher2013-12-241-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: re-order firmware loading in preparation for dpm reworkAlex Deucher2013-12-241-20/+22
|/ | | | | | | | We need to reorder the driver init sequence to better accomodate dpm which needs to be loaded earlier in the init sequence. Move fw init up so that it's available for dpm init. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: Add macrotile mode array queryMichel Dänzer2013-11-181-0/+3
| | | | | | | | This is required to properly calculate the tiling parameters in userspace. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use a single doorbell for cik kms computeAndrew Lewycky2013-11-151-20/+16
| | | | | | | | | | A single doorbell page is plenty for cik kms compute. Use a single page and manage doorbell allocation by individual doorbells rather than pages. Identify doorbells by their index rather than byte offset. Signed-off-by: Andrew Lewycky <Andrew.Lewycky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: disable CIK CP semaphores for nowChristian König2013-11-151-0/+5
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: allow semaphore emission to failChristian König2013-11-151-8/+5
| | | | | | | | | To workaround bugs and/or certain limits it's sometimes useful to fall back to waiting on fences. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: update cik_get_csb_buffer for hawaiiAlex Deucher2013-11-081-0/+4
| | | | | | | Set the PA_SC_RASTER_CONFIG[_1] registers for hawaii. The rest is the same as the other asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update firmware loading for hawaiiAlex Deucher2013-11-081-3/+58
| | | | | | | | This just updates the firmware loading functions to look for the appropriate firmware files for hawaii. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update rb setup for hawaiiAlex Deucher2013-11-081-1/+10
| | | | | | | The formula needs to be adjusted since there are 4 RBs per SH rather than 2 as on previous asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add golden register settings for hawaiiAlex Deucher2013-11-081-0/+179
| | | | | | | The golden register settings are optimal settings for certain registers from the hardware team. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update cik_tiling_mode_table_init() for hawaiiAlex Deucher2013-11-081-2/+220
| | | | | | | Hawaii uses a different tiling configuration. Add support for it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: minor updates to cik.c for hawaiiAlex Deucher2013-11-081-2/+8
| | | | | | | Skip programming a register that was removed and adjust the mask of the VM client status. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update cik_gpu_init() for hawaiiAlex Deucher2013-11-081-0/+17
| | | | | | | This adds the hawaii asic specific configuration details. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge tag 'drm-intel-fixes-2013-11-07' of ↵Dave Airlie2013-11-081-0/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~danvet/drm-intel into drm-next Bit a bit -fixes pull request in the merge window than usual dua to two feauture-y things: - Display CRCs are now enabled on all platforms, including the odd DP case on gm45/vlv. Since this is a testing-only feature it should ever hurt, but I figured it'll help with regression-testing -fixes. So I left it in and didn't postpone it to 3.14. - Display power well refactoring from Imre. Would have caused major pain conflict with the bdw stage 1 patches if I'd postpone this to -next. It's only an relatively small interface rework, so shouldn't cause pain. It's also been in my tree since almost 3 weeks already. That accounts for about two thirds of the pull, otherwise just bugfixes: - vlv backlight fix from Jesse/Jani - vlv vblank timestamp fix from Jesse - improved edp detection through vbt from Ville (fixes a vlv issue) - eDP vdd fix from Paulo - fixes for dvo lvds on i830M - a few smaller things all over Note: This contains a backmerge of v3.12. Since the -internal branch always applied on top of -nightly I need that unified base to merge bdw patches. So you'll get a conflict with radeon connector props when pulling this (and nouveau/master will also conflict a bit when Ben doesn't rebase). The backmerge itself only had conflicts in drm/i915. There's also a tiny conflict between Jani's backlight fix and your sysfs lifetime fix in drm-next. * tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits) drm/i915/vlv: use per-pipe backlight controls v2 drm/i915: make backlight functions take a connector drm/i915: move opregion asle request handling to a work queue drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV drm/i915: Make intel_dp_is_edp() less specific drm/i915: Give names to the VBT child device type bits drm/i915/vlv: enable HDA display audio for Valleyview2 drm/i915/dvo: call ->mode_set callback only when the port is running drm/i915: avoid unclaimed registers when capturing the error state drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv drm/i915: scramble reset support for DP port CRC on vlv drm/i915: scramble reset support for DP port CRC on g4x drm/i916: add "auto" pipe CRC source ... Conflicts: MAINTAINERS drivers/gpu/drm/i915/intel_panel.c drivers/gpu/drm/nouveau/core/subdev/mc/base.c drivers/gpu/drm/radeon/atombios_encoders.c drivers/gpu/drm/radeon/radeon_connectors.c
| * drm/radeon: make missing smc ucode non-fatal (CI)Alex Deucher2013-10-181-0/+1
| | | | | | | | | | | | | | | | | | Prevent driver load problems if the smc is missing. bug: https://bugzilla.kernel.org/show_bug.cgi?id=63011 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: stop the leaks in cik_ib_testChristian König2013-10-181-0/+3
| | | | | | | | | | | | | | Stop leaking IB memory and scratch register space when the test fails. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: improve soft reset on CIKAlex Deucher2013-10-091-0/+6
| | | | | | | | | | | | Disable CG/PG before resetting. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: drop CP page table updates & cleanup v2Christian König2013-11-011-61/+0
| | | | | | | | | | | | | | | | | | The DMA ring seems to be stable now. v2: remove pt_ring_index as well Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: don't use PACKET2 on CIKMarek Olšák2013-11-011-1/+1
| | | | | | | | | | | | | | | | It is said to cause hangs. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: fix endian handling in rlc buffer setupAlex Deucher2013-11-011-23/+24
| | | | | | | | | | | | | | The buffers needs to be in little endian format. Noticed-by: Sylvain BERTRAND <sylware@legeek.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: implement blit copy callback for CIKAlex Deucher2013-11-011-0/+79
| | | | | | | | | | | | | | Uses the CP ring rather than the DMA ring. Useful for debugging and benchmarking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: add a connector property for ditherAlex Deucher2013-11-011-5/+8
| | | | | | | | | | | | | | | | Allows you to enable dither in the display hardware when the monitor supports lower a lower bpc than the current framebuffer format. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: Add support for programming the FMT blocksAlex Deucher2013-11-011-0/+61
|/ | | | | | | | | | | | The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: fix overflow in vram fetchAlex Deucher2013-09-241-2/+2
| | | | | | | | Missing ULL when calculating the amount of vram leads to an overflow when the amount of vram is >= 4G. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon/cik: Fix encoding of number of banks in tiling configuration infoMichel Dänzer2013-09-201-4/+2
| | | | | | | | | There are multiple valid values, not just 0 or 1. Required to properly support 2D tiling in the userspace drivers. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: Fix printing of client name on VM protection faultMichel Dänzer2013-09-201-3/+4
| | | | | | | | The string is encoded from the MSB to the LSB of the register. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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