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* Merge tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremapLinus Torvalds2020-01-272-2/+2
|\ | | | | | | | | | | | | | | | | | | Pull ioremap updates from Christoph Hellwig: "Remove the ioremap_nocache API (plus wrappers) that are always identical to ioremap" * tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap: remove ioremap_nocache and devm_ioremap_nocache MIPS: define ioremap_nocache to ioremap
| * remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig2020-01-062-2/+2
| | | | | | | | | | | | | | | | ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
* | mmc: core: Default to generic_cmd6_time as timeout in __mmc_switch()Ulf Hansson2020-01-241-14/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | All callers of __mmc_switch() should now be specifying a valid timeout for the CMD6 command. However, just to be sure, let's print a warning and default to use the generic_cmd6_time in case the provided timeout_ms argument is zero. In this context, let's also simplify some of the corresponding code and clarify some related comments. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20200122142747.5690-4-ulf.hansson@linaro.org
* | mmc: block: Use generic_cmd6_time when modifying INAND_CMD38_ARG_EXT_CSDUlf Hansson2020-01-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The INAND_CMD38_ARG_EXT_CSD is a vendor specific EXT_CSD register, which is used to prepare an erase/trim operation. However, it doesn't make sense to use a timeout of 10 minutes while updating the register, which becomes the case when the timeout_ms argument for mmc_switch() is set to zero. Instead, let's use the generic_cmd6_time, as that seems like a reasonable timeout to use for these cases. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20200122142747.5690-3-ulf.hansson@linaro.org
* | mmc: core: Specify timeouts for BKOPS and CACHE_FLUSH for eMMCUlf Hansson2020-01-241-3/+6
| | | | | | | | | | | | | | | | | | | | | | The timeout values used while waiting for a CMD6 for BKOPS or a CACHE_FLUSH to complete, are not defined by the eMMC spec. However, a timeout of 10 minutes as is currently being used, is just silly for both of these cases. Instead, let's specify more reasonable timeouts, 120s for BKOPS and 30s for CACHE_FLUSH. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20200122142747.5690-2-ulf.hansson@linaro.org
* | mmc: sdhci-cadence: remove unneeded 'inline' markerMasahiro Yamada2020-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'static inline' in .c files does not make much sense because functions may or may not be inlined irrespective of the 'inline' marker. It is just a hint. This function is quite small, so very likely to be inlined by the compiler's optimization (-O2 or -Os), but it is up to the compiler after all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200121105858.13325-1-yamada.masahiro@socionext.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-msm: Add CQHCI support for sdhci-msmRitesh Harjani2020-01-242-1/+133
| | | | | | | | | | | | | | | | | | | | This adds CQHCI support for sdhci-msm platforms. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1579194192-7942-3-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: Let a vendor driver supply and update ADMA descriptor sizeVeerabhadrarao Badiganti2020-01-242-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let a vendor driver supply the maximum descriptor size that it can operate on. ADMA descriptor table would be allocated using this supplied size. If any SD Host controller is of version prior to v4.10 spec but supports 16byte descriptor, this change allows them to supply correct descriptor size for ADMA table allocation. Also let a vendor driver update the descriptor size by overriding sdhc_host->desc_size if it has to operates on a different descriptor sizes in different conditions. Suggested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1579531122-28341-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: fix serious issue clock is always disabledYangbo Lu2020-01-201-1/+1
| | | | | | | | | | | | | | | | | | | | This patch is to fix a serious issue that clock is always disabled in esdhc_of_set_clock(). Fixes: 1b21a701aed9 ("mmc: sdhci-of-esdhc: fix clock setting for different controller versions") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lore.kernel.org/r/20200120094835.28050-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: fix transfer mode register readingYangbo Lu2020-01-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The standard SD controller uses two 16-bit registers for command sending. 0xC: Transfer Mode Register 0xE: Command Register But the eSDHC controller uses one 32-bit register instead. 0xC: XFERTYPE For Transfer Mode Register and Command Register writing, the eSDHC driver will store Transfer Mode Register value in a variable first. When Command Register writing happens, driver will directly write a 32-bit value into XFERTYPE register. But for Transfer Mode Register reading, driver just returns a actual value. This may cause issue for some read-modify-write operations. We should make both reading and write on that variable for Transfer Mode Register. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lore.kernel.org/r/20200117063858.37296-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-brcmstb: Fix incorrect switch to HS modeAl Cooper2020-01-201-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. This issue was previously fixed by commit c894e33ddc191 ("mmc: sdhci: Fix incorrect switch to HS mode") and later removed by commit 07bcc411567c ("Revert \"mmc: sdhci: Fix incorrect switch to HS mode\"") because it caused failures with some SD cards on AM65X systems. The fix will now be done in a platform specific callback instead of common sdhci code. Signed-off-by: Al Cooper <alcooperx@gmail.com> Suggested-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200113210706.11972-7-alcooperx@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)Al Cooper2020-01-202-8/+133
| | | | | | | | | | | | | | | | | | The latest Arasan controller first used in the 7216 now supports CQE so enable this feature. Signed-off-by: Al Cooper <alcooperx@gmail.com> Link: https://lore.kernel.org/r/20200113210706.11972-6-alcooperx@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-brcmstb: Add shutdown callbackAl Cooper2020-01-201-0/+10
| | | | | | | | | | | | | | | | | | Shutdown controller and disable it's clocks to insure max power savings in S5 on systems that leave power on. Signed-off-by: Al Cooper <alcooperx@gmail.com> Link: https://lore.kernel.org/r/20200113210706.11972-5-alcooperx@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-brcmstb: Fix driver to defer on clk_get deferAl Cooper2020-01-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new SCMI clock protocol driver does not get probed that early in boot. Brcmstb drivers typically have the following code when getting a clock: priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "Clock not found in Device Tree\n"); priv->clk = NULL; } This commit changes the driver to do what is below. priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { if (PTR_ERR(priv->clk) == -EPROBE_DEFER) return -EPROBE_DEFER; dev_err(&pdev->dev, "Clock not found in Device Tree\n"); priv->clk = NULL; } Signed-off-by: Al Cooper <alcooperx@gmail.com> Link: https://lore.kernel.org/r/20200113210706.11972-4-alcooperx@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-brcmstb: Add ability to use HS400ES transfer modeAl Cooper2020-01-201-11/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest eMMC JEDEC specification version 5.1 added a new transfer mode, HS400 with enhanced strobe (HS400ES). This mode will be selected if both the host controller and eMMC device support it. The latest Arasan 5.1 controller in the 7216a0 supports this mode. The "Host Controller Specification" has not been updated so the controller register bit used to enable this mode is not specified and varies the with controller vendor. The Linux SDHCI driver supplies a callback for enabling HS400ES mode and that callback will be used to supply a routine that will set the proper bit in the Arasan Vendor register. Signed-off-by: Al Cooper <alcooperx@gmail.com> Link: https://lore.kernel.org/r/20200113210706.11972-3-alcooperx@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: core: limit probe clock frequency to configured f_maxMichał Mirosław2020-01-201-2/+8
| | | | | | | | | | | | | | | | | | | | Currently MMC core disregards host->f_max during card initialization phase. Obey upper boundary for the clock frequency and skip faster speeds when they are above the limit. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/f471bceaf237d582d746bd289c4c4f3639cb7b45.1577962382.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-milbeaut: Remove redundant platform_get_irq error messageYueHaibing2020-01-201-3/+1
| | | | | | | | | | | | | | | | | | | | | | platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116144322.57308-1-yuehaibing@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: fix an issue of mixing different typesChunyan Zhang2020-01-201-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix an issue reported by sparse, since mixed types of parameters are used on calling dmaengine_prep_slave_sg(). Fixes: 36e1da441fec (mmc: sdhci: add support for using external DMA devices) Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200120033223.897-1-zhang.chunyan@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | Merge branch 'fixes' into nextUlf Hansson2020-01-202-5/+7
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| * | mmc: sdhci: fix minimum clock rate for v3 controllerMichał Mirosław2020-01-201-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SDHCIv3+ with programmable clock mode, minimal clock frequency is still base clock / max(divider). Minimal programmable clock frequency is always greater than minimal divided clock frequency. Without this patch, SDHCI uses out-of-spec initial frequency when multiplier is big enough: mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz [for 480 MHz source clock divided by 1024] The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode. Fixes: c3ed3877625f ("mmc: sdhci: add support for programmable clock mode") Cc: <stable@vger.kernel.org> # 4f6aa3264af4: mmc: tegra: Only advertise UHS modes if IO regulator is present Cc: <stable@vger.kernel.org> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: tegra: fix SDR50 tuning overrideMichał Mirosław2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7ad2ed1dfcbe inadvertently mixed up a quirk flag's name and broke SDR50 tuning override. Use correct NVQUIRK_ name. Fixes: 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") Cc: <stable@vger.kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/9aff1d859935e59edd81e4939e40d6c55e0b55f6.1578390388.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-omap: Add special reset capabilityFaiz Abbas2020-01-201-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some omap controllers need software to monitor a 0->1->0 for software reset. Add a SDHCI_OMAP_SPECIAL_RESET flag to indicate this. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-11-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-omap: Add am335x and am437x specific compatiblesFaiz Abbas2020-01-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for new compatible for TI's am335x and am437x devices. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-10-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-omap: Disable data timeout interrupt during eraseFaiz Abbas2020-01-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Disable data timeout interrupt during an erase operation. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-8-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: Refactor sdhci_set_timeout()Faiz Abbas2020-01-202-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor sdhci_set_timeout() such that platform drivers can do some functionality in a set_timeout() callback and then call __sdhci_set_timeout() to complete the operation. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-7-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: Convert sdhci_set_timeout_irq() to non-staticFaiz Abbas2020-01-202-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Export sdhci_set_timeout_irq() so that it is accessible from platform drivers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-6-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-omap: Add using external dmaChunyan Zhang2020-01-202-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdhci-omap can support both external dma controller via dmaengine framework as well as ADMA which standard SD host controller provides. Fixes by Faiz Abbas <fazi_abbas@ti.com>: 1. Switch to DMA slave mode when using external DMA 2. Add offset to mapbase Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-5-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: add support for using external DMA devicesChunyan Zhang2020-01-203-2/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some standard SD host controllers can support both external dma controllers as well as ADMA/SDMA in which the SD host controller acts as DMA master. TI's omap controller is the case as an example. Currently the generic SDHCI code supports ADMA/SDMA integrated in the host controller but does not have any support for external DMA controllers implemented using dmaengine, meaning that custom code is needed for any systems that use an external DMA controller with SDHCI. Fixes by Faiz Abbas <faiz_abbas@ti.com>: 1. Map scatterlists before dmaengine_prep_slave_sg() 2. Use dma_async() functions inside of the send_command() path and call terminate_sync() in non-atomic context in case of an error. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: Factor out some operations set to their own functionsFaiz Abbas2020-01-201-41/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding external dma support, factor out data initialization, block info and mrq_done to their own functions. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Tested-by: Baolin Wang <baolin.wang7@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-of-at91: fix memleak on clk_get failureMichał Mirosław2020-01-161-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdhci_alloc_host() does its work not using managed infrastructure, so needs explicit free on error path. Add it where needed. Cc: <stable@vger.kernel.org> Fixes: bb5f8ea4d514 ("mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC") Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/b2a44d5be2e06ff075f32477e466598bb0f07b36.1577961679.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | Merge branch 'fixes' into nextUlf Hansson2020-01-161-19/+35
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| * | mmc: sdhci_am654: Fix Command Queuing in AM65xFaiz Abbas2020-01-161-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Command Queuing was enabled completely for J721e controllers which lead to partial enablement even for Am65x. Complete CQ implementation for AM65x by adding the irq callback. Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Cc: stable@vger.kernel.org Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108143301.1929-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci_am654: Reset Command and Data line after tuningFaiz Abbas2020-01-161-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tuning data is leftover in the buffer after tuning. This can cause issues in future data commands, especially with CQHCI. Reset the command and data lines after tuning to continue from a clean state. Fixes: 41fd4caeb00b ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driver") Cc: stable@vger.kernel.org Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108143301.1929-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci_am654: Remove Inverted Write Protect flagFaiz Abbas2020-01-161-6/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC/SD controllers on am65x and j721e don't in fact detect the write protect line as inverted. No issues were detected because of this because the sdwp line is not connected on any of the evms. Fix this by removing the flag. Fixes: 1accbced1c32 ("mmc: sdhci_am654: Add Support for 4 bit IP on J721E") Cc: stable@vger.kernel.org Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108143301.1929-2-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: fix clock setting for different controller versionsYangbo Lu2020-01-161-56/+72
| | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix clock setting code for different controller versions. Two of HW changes after vendor version 2.2 are removing PEREN/HCKEN/IPGEN bits in system control register, and adding SD clock stable bit in present state register. This patch cleans up related code too. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lore.kernel.org/r/20200108040713.38888-2-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller versionsYangbo Lu2020-01-161-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix operating in esdhc_reset() for different controller versions, and to add bus-width restoring after data reset for eSDHC (verdor version <= 2.2). Also add annotation for understanding. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108040713.38888-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: update tuning erratum A-008171Yangbo Lu2020-01-161-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an official update for eSDHC tuning erratum A-008171. This patch is to implement the changes, - Affect all revisions of SoC. - Changes for tuning window checking. - Hardware hits a new condition that tuning succeeds although the eSDHC might not have tuned properly for type2 SoCs (soc_tuning_erratum_type2[] array in driver). So check tuning window after tuning succeeds. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191212075219.48625-2-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: convert to use esdhc_tuning_window_ptr()Yangbo Lu2020-01-161-13/+21
| | | | | | | | | | | | | | | | | | | | Convert to use a new function esdhc_tuning_window_ptr() to get tuning window start point and end point. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191212075219.48625-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: bcm2835: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20191217122254.7103-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: usdhi6rol0: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA if needed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217113114.32085-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sh_mmcif: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA if needed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217113031.31847-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: pxamci: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217113004.31688-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: owl-mmc: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217112934.31535-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: mxs: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217112847.31351-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: mxcmmc: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217112803.31161-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: mmci: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217112737.31024-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: dw_mmc: Use dma_request_chan() instead dma_request_slave_channel()Peter Ujfalusi2019-12-191-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() is a wrapper on top of dma_request_chan() eating up the error code. By using dma_request_chan() directly the driver can support deferred probing against DMA. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191217112656.30860-1-peter.ujfalusi@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | Merge branch 'fixes' into nextUlf Hansson2019-12-191-0/+10
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| * mmc: sdhci-of-esdhc: re-implement erratum A-009204 workaroundYangbo Lu2019-12-191-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The erratum A-009204 workaround patch was reverted because of incorrect implementation. 8b6dc6b mmc: sdhci-of-esdhc: Revert "mmc: sdhci-of-esdhc: add erratum A-009204 support" This patch is to re-implement the workaround (add a 5 ms delay before setting SYSCTL[RSTD] to make sure all the DMA transfers are finished). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lore.kernel.org/r/20191219032335.26528-1-yangbo.lu@nxp.com Fixes: 5dd195522562 ("mmc: sdhci-of-esdhc: add erratum A-009204 support") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: mmci: Support any block sizes for ux500v2 and qcom variantLinus Walleij2019-12-182-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the ux500v2 variant of the PL18x block, any block sizes are supported. This is necessary to support some SDIO transfers. This also affects the QCOM MMCI variant and the ST micro variant. For Ux500 an additional quirk only allowing DMA on blocks that are a power of two is needed. This might be a bug in the DMA engine (DMA40) or the MMCI or in the interconnect, but the most likely is the MMCI, as transfers of these sizes work fine for other devices using the same DMA engine. DMA works fine also with SDIO as long as the blocksize is a power of 2. This patch has proven necessary for enabling SDIO for WLAN on PostmarketOS-based Ux500 platforms. What we managed to test in practice is Broadcom WiFi over SDIO on the Ux500 based Samsung GT-I8190 and GT-S7710. This WiFi chip, BCM4334 works fine after the patch. Before this patch: brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac4334-sdio for chip BCM4334/3 mmci-pl18x 80118000.sdi1_per2: unsupported block size (60 bytes) brcmfmac: brcmf_sdiod_ramrw: membytes transfer failed brcmfmac: brcmf_sdio_download_code_file: error -22 on writing 434236 membytes at 0x00000000 brcmfmac: brcmf_sdio_download_firmware: dongle image file download failed After this patch: brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM4334/3 wl0: Nov 21 2012 00:21:28 version 6.10.58.813 (B2) FWID 01-0 Bringing up networks, discovering networks with "iw dev wlan0 scan" and connecting works fine from this point. This patch is inspired by Ulf Hansson's patch http://www.spinics.net/lists/linux-mmc/msg12160.html As the DMA engines on these platforms may now get block sizes they were not used to before, make sure to also respect if the DMA engine says "no" to a transfer. Make a drive-by fix for datactrl_blocksz, misspelled. Cc: Ludovic Barre <ludovic.barre@st.com> Cc: Brian Masney <masneyb@onstation.org> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Niklas Cassel <niklas.cassel@linaro.org> Cc: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191217143952.2885-1-linus.walleij@linaro.org
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