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path: root/drivers/pinctrl/pinctrl-zynq.c
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* pinctrl: zynq: Fix warnings in the driverNava kishore Manne2017-08-141-16/+16
| | | | | | | | | | | This patch fixes the below warning --> Prefer 'unsigned int' to bare use of 'unsigned'. --> line over 80 characters. --> Prefer 'unsigned int **' to bare use of 'unsigned **'. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: Fix kernel doc warningsNava kishore Manne2017-08-141-1/+1
| | | | | | | | This patch fixes the kernel doc warnings in the driver. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: Add a 8 bit wide nand optionJason Gunthorpe2016-11-041-1/+5
| | | | | | | | | The hardware supports a 16 and 8 bit wide NAND bus, let users pick either. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix typo in sdio1_3_grp pin listDaniel Glöckner2016-09-061-1/+1
| | | | | | | | It contains pin 50 instead of pin 40. Signed-off-by: Daniel Glöckner <dg@emlix.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: make it explicitly non-modularPaul Gortmaker2016-06-131-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: config PINCTRL_ZYNQ bool "Pinctrl driver for Xilinx Zynq" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann" <soren.brinkmann@xilinx.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registrationLaxman Dewangan2016-04-211-11/+1
| | | | | | | | | | | | | Use devm_pinctrl_register() for pin control registration and remove the need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_mapIrina Tirdea2016-04-011-1/+1
| | | | | | | | | | | Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since it does not depend on device tree despite the current name. This will enforce a consistent naming in pinctr-utils.c and will make it clear it can be called from outside device tree (e.g. from ACPI handling code). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix typo in group name for qspi1Helmut Buchsbaum2016-02-151-1/+1
| | | | | | | | | | | | | Due to a typo Zynq pin controller does not set pin function of qspi1 when using function qspi1. So pin group for qspi1 has to be renamed to "qspi1_0_grp" as outlined in the corresponding bindings documentation. This also removes kernel message: zynq-pinctrl 700.pinctrl: invalid group "qspi1_0_grp" for function "qspi1" Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix UTF-8 errorsLinus Walleij2015-10-311-2/+2
| | | | | | | Fix up Sören's name in the Zynq driver. I caused this. I fix it. Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: Initialize earlyMike Looijmans2015-10-301-1/+11
| | | | | | | | | | | Supplying pinmux configuration for e.g. gpio pins leads to deferred probes because the pinctrl device is probed much later than gpio. Move the init call to a much earlier stage so it probes before the devices that may need it. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grpMike Looijmans2015-08-251-2/+2
| | | | | | | | | | | | | Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll get errors like this if you try to pinmux them via the devicetree: zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand" Probably a typo while creating these tables. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: make pinctrl_register() return proper error codeMasahiro Yamada2015-06-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Ray Jui <rjui@broadcom.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: add static const to zynq_pctrl_groupsMasahiro Yamada2015-06-021-1/+1
| | | | | | | | This array is only referenced in this file and never updated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: add static to zynq_pinsMasahiro Yamada2015-06-021-1/+1
| | | | | | | This array is only referenced in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SELMasahiro Yamada2015-06-011-4/+4
| | | | | | | | | | | | The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, 0xf8000834, respectively. Each offset address must be prefixed with 0x. Fixes: add958cee967 "pinctrl: Add driver for Zynq" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macroMasahiro Yamada2015-06-011-1/+2
| | | | | | | | | The offset to the mux register is missing. Fixes: add958cee967 "pinctrl: Add driver for Zynq" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: add static to platform_driver remove callbackMasahiro Yamada2015-05-191-1/+1
| | | | | | | | This function is only referenced in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: configure SPI SSx pins separatelyHelmut Buchsbaum2015-05-061-7/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI interfaces, SS0, SS1 and SS2 have to be configured separately as they may be used as simple GPIO lines. This, of course, has to be considered in the devicetree, so pin controller configuration for e.g. an SPI0 using SS0 and SS1 only might look like the following snippet (derived from the example of chapter "17.5.3 MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used as GPIO instead of being occupied by SPI0 SS2 function. Note the separate pinmux function for the slave select signals: pinctrl_spi0_default: spi0-default { mux_spi { function = "spi0"; groups = "spi0_0_grp"; }; mux_ss { function = "spi0_ss"; groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp"; } conf-output { pins = "MIO16", "MIO21"; slew-rate = <0>; bias-disable; low-power-disable; io-standard = <1>; }; conf-input { pins = "MIO17"; slew-rate = <0>; bias-high-impedance; low-power-disable; io-standard = <1>; }; conf-select { pins = "MIO18", "MIO19"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; pinctrl_gpio0_default { mux { function = "gpio0"; groups = "gpio0_20_grp" }; conf { pins = "MIO20"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: hide PCONFDUMP in #ifdefArnd Bergmann2015-01-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | The zynq and qcom-spmi pinctrl drivers both use pin_config_item arrays to provide extra interfaces in debugfs. This structure and the PCONFDUMP macro are not defined if CONFIG_DEBUG_FS is turned off, so we get build errors like: pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: error: array type has incomplete element type static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { ^ pinctrl/qcom/pinctrl-spmi-gpio.c:140:2: error: implicit declaration of function 'PCONFDUMP' [-Werror=implicit-function-declaration] PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), ^ pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: warning: 'pmic_conf_items' defined but not used [-Wunused-variable] static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { Lacking any better idea to solve this nicely, this patch uses #ifdef to hide the structures, just like the pinctrl core does. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: Fix usb0 pinsAndreas Färber2015-01-301-1/+1
| | | | | | | | | | Fix usb0 pin 19 -> 29 (matching ethernet1 pins and manual). Pin 19 is used for ethernet0 on the Parallella board. Fixes: add958cee967 ("pinctrl: Add driver for Zynq") Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinconf-generic: loose DT dependenceLinus Walleij2015-01-141-4/+4
| | | | | | | | | | | | | New pin controllers such as ACPI-based may also have custom properties to parse, and should be able to use generic pin config. Let's make the code compile on !OF systems and rename members a bit to underscore it is custom parameters and not necessarily DT parameters. This fixes a build regression for x86_64 on the zeroday kernel builds. Reported-by: kbuild test robot <fengguang.wu@intel.com> Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add driver for ZynqSoren Brinkmann2015-01-111-0/+1176
This adds a pin-control driver for Zynq. Changes since v2: - driver-specific DT properties are passed to the core in two arrays, one for the actual DT parsing one for the debugfs representation. Issue a compiler warning when the number of entries is not the same for both arrays. Changes since v1: - fix EMIO_SD1_CD pin name - add USB to pinmux options changes since RFCv2: - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is present in DT but no driver available. - add #defines to get rid of magical constants - add commas at end of initializers - separate changes in mach-zynq in separate patch - add driver specific io-standard DT property - refactored pinconf set function to not require arguments for argument-less properties - squash other patches in - support for IO-standard property - support for low-power mode property - migration to pinconf_generic_dt_node_to_map_all() - use newly created infrastructure to add pass driver-specific DT params to pinconf-generic changes since RFC: - use syscon/regmap to access registers in SLCR space - rebase to 3.18: rename enable -> set_mux - add kernel-doc - support pinconf - supported attributes - pin-bias: pull up, tristate, disable - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display argument Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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