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* Merge tag 'pinctrl-v5.13-1' of ↵Linus Torvalds2021-04-305-4/+175
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is a lot going on! Core changes: - A semantic change to handle pinmux and pinconf in explicit order while up until now we depended on the semantic order in the device tree. The device tree is a functional programming language and does not imply any order, so the right thing is for the pin control core to provide these semantics. - Add a new pinmux-select debugfs file which makes it possible to go in and select functions for a pin manually (iteratively, at the prompt) for debugging purposes. - Fixes to gpio regmap handling for a new pin control driver making use of regmap-gpio. - Use octal permissions on debugfs files. New drivers: - A massive rewrite of the former custom pin control driver for MIPS Broadcom devices to instead use the pin control subsystem. New pin control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368, BCM63268 and BCM6318 SoC variants are implemented. - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are supported. - Support for the Rockchip RK3568/RK3566 pin controller. - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000. - Support for Mediatek MTK8195. - Add a new Xilinx ZynqMP pin control driver. Driver improvements and non-urgent fixes: - Modularization and improvements of the Rockchip drivers. - Some new pins added to the description of new Renesas SoCs. - Clarifications of the GPIO base calculation in the Intel driver. - Fix the function names for the MPP54 and MPP55 pins in the Armada CP110 pin controller. - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350. - Support for ACPI probing of the Qualcomm SC8180x. - Fix interrupt clear status on rockchip - Fix some missing pins on the Ingenic JZ4770, some semantic fixes for the behaviour of the Ingenic pin controller. Add DMIC pins for JZ4780, X1000, X1500 and X1830. - A slew of janitorial like of_node_put() calls" * tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: Add Xilinx ZynqMP pinctrl driver support firmware: xilinx: Add pinctrl support pinctrl: rockchip: do coding style for mux route struct pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param pinctrl: Introduce MODE group in enum pin_config_param pinctrl: Keep enum pin_config_param ordered by name dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver pinctrl: core: Fix kernel doc string for pin_get_name() pinctrl: mediatek: use spin lock in mtk_rmw pinctrl: add drive for I2C related pins on MT8195 pinctrl: add pinctrl driver on mt8195 dt-bindings: pinctrl: mt8195: add pinctrl file and binding document pinctrl: Ingenic: Add pinctrl driver for X2000. pinctrl: Ingenic: Add pinctrl driver for JZ4775. pinctrl: Ingenic: Add pinctrl driver for JZ4755. pinctrl: Ingenic: Add pinctrl driver for JZ4750. pinctrl: Ingenic: Add pinctrl driver for JZ4730. dt-bindings: pinctrl: Add bindings for new Ingenic SoCs. pinctrl: Ingenic: Reformat the code. pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs. ...
| * drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIBJulian Braha2021-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When PINCTRL_MSM is enabled, and GPIOLIB is disabled, Kbuild gives the following warning: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_MSM [=y] && PINCTRL [=y] && (ARCH_QCOM || COMPILE_TEST [=y]) This is because PINCTRL_MSM selects GPIOLIB_IRQCHIP, without selecting or depending on GPIOLIB, despite GPIOLIB_IRQCHIP depending on GPIOLIB. Having PINCTRL_MSM select GPIOLIB will cause a recursive dependency error. Signed-off-by: Julian Braha <julianbraha@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210414025138.480085-1-julianbraha@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom-pmic-gpio: Add support for pm8008Guru Das Srinagesh2021-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | Add support for the two GPIOs present on Qualcomm Technologies, Inc. PM8008. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org> Link: https://lore.kernel.org/r/129d241ee510e28536d35dbfeee75474e12d8d22.1617901945.git.gurus@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: sc8180x: add ACPI probe supportShawn Guo2021-03-152-3/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds ACPI probe support for pinctrl-sc8180x driver. We have one problem with ACPI table, i.e. GIO0 (TLMM) block has one single memory resource to cover 3 tiles defined by SC8180X. To follow the hardware layout of 3 tiles which is already supported DT probe, it adds one function to replace the original single memory resource with 3 named ones for tiles. With that, We can map memory for ACPI in the same way as DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210311024102.15450-1-shawn.guo@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: sm8350: add GPIO wakeup interrupt mapLina Iyer2021-03-151-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Provide the interrupt map of the GPIO to its wakeup capable interrupt parent. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312034218.3324410-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-gpio: Add support for PM8350 and friendsVinod Koul2021-03-151-0/+6
| | | | | | | | | | | | | | | | | | | | Add support for the PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B GPIO support to the Qualcomm PMIC GPIO driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210308164845.3210393-2-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: sc7280: Add GPIO wakeup interrupt mapMaulik Shah2021-03-101-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Provide the interrupt map of the GPIO to its wakeup capable interrupt parent. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1613105974-28181-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: fix unintentional string concatenationArnd Bergmann2021-03-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang is clearly correct to point out a typo in a silly array of strings: drivers/pinctrl/qcom/pinctrl-sdx55.c:426:61: error: suspicious concatenation of string literals in an array initialization; did you mean to separate the elements with a comma? [-Werror,-Wstring-concatenation] "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19" "gpio20", "gpio21", "gpio22", ^ Add the missing comma that must have accidentally been removed. Fixes: ac43c44a7a37 ("pinctrl: qcom: Add SDX55 pincontrol driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20210323131728.2702789-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: sc7280: Fix SDC1_RCLK configurationsRajendra Nayak2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix SDC1_RCLK configurations which are in a different register so fix the offset from 0xb3000 to 0xb3004. Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver") Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1614662511-26519-2-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: sc7280: Fix SDC_QDSD_PINGROUP and UFS_RESET offsetsRajendra Nayak2021-03-111-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | The offsets for SDC_QDSD_PINGROUP and UFS_RESET were off by 0x100000 due to an issue in the scripts generating the data. Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver") Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1614662511-26519-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: lpass lpi: use default pullup/strength valuesJonathan Marek2021-03-111-1/+1
|/ | | | | | | | | | | | | | | | | | If these fields are not set in dts, the driver will use these variables uninitialized to set the fields. Not only will it set garbage values for these fields, but it can overflow into other fields and break those. In the current sm8250 dts, the dmic01 entries do not have a pullup setting, and might not work without this change. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210304194816.3843-1-jonathan@marek.ca Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.12-1' of ↵Linus Torvalds2021-02-227-2/+3294
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.12 kernel. This time a calm set with no core changes. New drivers/subdrivers: - Renesas R8A7790A0 pin controller. - Allwinner H616 and H616-R pin controllers. - Qualcomm SM8350 and SC8180x pin controllers. Improvements: - Redo the DT bindings for Ralink RT2880. - A common Qualcomm TLMM DT binding in YAML. - Delete the unused drivers for U300, COH901, Sirf Atlas, and ZTE ZX" * tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt dt-bindings: pinctrl: Group tuples in pin control properties pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'" pinctrl: at91-pio4: add support for slew-rate dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: actions: Add depends on || COMPILE_TEST pinctrl: single: set function name when adding function pinctrl: qcom: Add sc8180x TLMM driver dt-bindings: pinctrl: qcom: Add sc8180x binding dt-bindings: pinctrl: qcom: Define common TLMM binding pinctrl: qcom: Add SM8350 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings pinctrl: samsung: use raw_spinlock for s3c64xx dt-bindings: mediatek: mt8192: Fix dt_binding_check warning pinctrl: qcom: spmi-mpp: Add PM8019 compatible pinctrl: pinmux: add function selector to pinmux-functions pinctrl: samsung: use raw_spinlock for locking pinctrl: clarify #pinctrl-cells for pinctrl-single,pins pinctrl: actions: Add the platform dependency to drivers ...
| * pinctrl: qcom: Add sc8180x TLMM driverBjorn Andersson2021-02-123-0/+1634
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver for the sc8180x TLMM block. A noteworthy difference from previous TLMM blocks is that the registers for GPIO 177 through 189 are for some reason offset from the typical layout. Other than that the driver is same old... Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126042650.1725176-3-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add SM8350 pinctrl driverVinod Koul2021-02-123-0/+1659
| | | | | | | | | | | | | | | | | | | | | | This adds pincontrol driver for tlmm block found in SM8350 SoC This patch is based on initial code downstream by Raghavendra. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210205140132.274242-3-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-mpp: Add PM8019 compatibleKonrad Dybcio2021-01-261-0/+1
| | | | | | | | | | | | | | | | | | PM8019 provides 6 MPPs. Add a compatible to support them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210115171115.123155-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: remove empty lines in pinctrl subsystemZhaoyu Liu2021-01-052-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove all empty lines at the end of functions in pinctrl subsystem, and make the code neat. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Zhaoyu Liu <zackaryliu@yeah.net> Link: https://lore.kernel.org/r/X98NP6NFK1Afzrgd@manjaro Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Don't clear pending interrupts when enablingDouglas Anderson2021-01-181-24/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Linux, if a driver does disable_irq() and later does enable_irq() on its interrupt, I believe it's expecting these properties: * If an interrupt was pending when the driver disabled then it will still be pending after the driver re-enables. * If an edge-triggered interrupt comes in while an interrupt is disabled it should assert when the interrupt is re-enabled. If you think that the above sounds a lot like the disable_irq() and enable_irq() are supposed to be masking/unmasking the interrupt instead of disabling/enabling it then you've made an astute observation. Specifically when talking about interrupts, "mask" usually means to stop posting interrupts but keep tracking them and "disable" means to fully shut off interrupt detection. It's unfortunate that this is so confusing, but presumably this is all the way it is for historical reasons. Perhaps more confusing than the above is that, even though clients of IRQs themselves don't have a way to request mask/unmask vs. disable/enable calls, IRQ chips themselves can implement both. ...and yet more confusing is that if an IRQ chip implements disable/enable then they will be called when a client driver calls disable_irq() / enable_irq(). It does feel like some of the above could be cleared up. However, without any other core interrupt changes it should be clear that when an IRQ chip gets a request to "disable" an IRQ that it has to treat it like a mask of that IRQ. In any case, after that long interlude you can see that the "unmask and clear" can break things. Maulik tried to fix it so that we no longer did "unmask and clear" in commit 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback"), but it only handled the PDC case and it had problems (it caused sc7180-trogdor devices to fail to suspend). Let's fix. >From my understanding the source of the phantom interrupt in the were these two things: 1. One that could have been introduced in msm_gpio_irq_set_type() (only for the non-PDC case). 2. Edges could have been detected when a GPIO was muxed away. Fixing case #1 is easy. We can just add a clear in msm_gpio_irq_set_type(). Fixing case #2 is harder. Let's use a concrete example. In sc7180-trogdor.dtsi we configure the uart3 to have two pinctrl states, sleep and default, and mux between the two during runtime PM and system suspend (see geni_se_resources_{on,off}() for more details). The difference between the sleep and default state is that the RX pin is muxed to a GPIO during sleep and muxed to the UART otherwise. As per Qualcomm, when we mux the pin over to the UART function the PDC (or the non-PDC interrupt detection logic) is still watching it / latching edges. These edges don't cause interrupts because the current code masks the interrupt unless we're entering suspend. However, as soon as we enter suspend we unmask the interrupt and it's counted as a wakeup. Let's deal with the problem like this: * When we mux away, we'll mask our interrupt. This isn't necessary in the above case since the client already masked us, but it's a good idea in general. * When we mux back will clear any interrupts and unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Fixes: 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210114191601.v7.4.I7cf3019783720feb57b958c95c2b684940264cd1@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Properly clear "intr_ack_high" interrupts when unmaskingDouglas Anderson2021-01-181-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") we tried to Ack interrupts during unmask. However, that patch forgot to check "intr_ack_high" so, presumably, it only worked for a certain subset of SoCs. Let's add a small accessor so we don't need to open-code the logic in both places. This was found by code inspection. I don't have any access to the hardware in question nor software that needs the Ack during unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.3.I32d0f4e174d45363b49ab611a13c3da8f1e87d0f@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: No need to read-modify-write the interrupt statusDouglas Anderson2021-01-181-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Qualcomm pinctrl driver wants to Ack an interrupt, it does a read-modify-write on the interrupt status register. On some SoCs it makes sure that the status bit is 1 to "Ack" and on others it makes sure that the bit is 0 to "Ack". Presumably the first type of interrupt controller is a "write 1 to clear" type register and the second just let you directly set the interrupt status register. As far as I can tell from scanning structure definitions, the interrupt status bit is always in a register by itself. Thus with both types of interrupt controllers it is safe to "Ack" interrupts without doing a read-modify-write. We can do a simple write. It should be noted that if the interrupt status bit _was_ ever in a register with other things (like maybe status bits for other GPIOs): a) For "write 1 clear" type controllers then read-modify-write would be totally wrong because we'd accidentally end up clearing interrupts we weren't looking at. b) For "direct set" type controllers then read-modify-write would also be wrong because someone setting one of the other bits in the register might accidentally clear (or set) our interrupt. I say this simply to show that the current read-modify-write doesn't provide any sort of "future proofing" of the code. In fact (for "write 1 clear" controllers) the new code is slightly more "future proof" since it would allow more than one interrupt status bits to share a register. NOTE: this code fixes no bugs--it simply avoids an extra register read. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.2.I3635de080604e1feda770591c5563bd6e63dd39d@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0Douglas Anderson2021-01-182-2/+3
|/ | | | | | | | | | | | | | | | There's currently a comment in the code saying function 0 is GPIO. Instead of hardcoding it, let's add a member where an SoC can specify it. No known SoCs use a number other than 0, but this just makes the code clearer. NOTE: no SoC code needs to be updated since we can rely on zero-initialization. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.11-1' of ↵Linus Torvalds2020-12-168-24/+5124
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.11 kernel. Drivers, drivers and drivers. Not a single core change. Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot SoCs. As part of the modularization attempt, I applied one patch affecting the firmware subsystem as a functional (not syntactic/semantic) dependency and then it blew up in our face, so I had to revert it, bummer. It will come in later, through that subsystem, I guess. New drivers: - New driver for the Microchip Serial GPIO "SGPIO". - Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver. New subdrivers: - Intel Lakefield subdriver. - Intel Elkhart Lake subdriver. - Intel Alder Lake-S subdriver. - Qualcomm MSM8953 subdriver. - Qualcomm SDX55 subdriver. - Qualcomm SDX55 PMIC subdriver. - Ocelot Luton SoC subdriver. - Ocelot Serval SoC subdriver. Modularization: - The Meson driver can now be built as modules. - The Qualcomm driver(s) can now be built as modules. Incremental improvements: - The Intel driver now supports pin configuration for GPIO-related configurations. - A bunch of Renesas PFC drivers have been augmented with support for QSPI pins, groups and functions. - Non-critical fixes to the irq handling in the Allwinner Sunxi driver" * tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl/spear: simplify the return expression of spear300_pinctrl_probe() pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1() dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5) pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom-pmic-gpio: Add support for pmx55 dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error pinctrl: mtk: Fix low level output voltage issue pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe() pinctrl: actions: pinctrl-s500: Constify s500_padinfo[] pinctrl: pinctrl-microchip-sgpio: Add OF config dependency pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver pinctrl: at91-pio4: add support for fewer lines on last PIO bank pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller ...
| * pinctrl: qcom: Add sm8250 lpass lpi pinctrl driverSrinivas Kandagatla2020-12-053-0/+707
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org [Add some dependencies] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom-pmic-gpio: Add support for pmx55Vinod Koul2020-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | PM55 pmic support gpio controller so add compatible and comment for gpio holes Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201126092151.1082697-2-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add sc7280 pinctrl driverRajendra Nayak2020-11-243-0/+1505
| | | | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration with pinctrl framework for SC7280 SoC Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1604570192-15057-2-git-send-email-rnayak@codeaurora.org [Change select PINCTRL_MSM to depends on PINCTRL_MSM] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Fix msm8953 Kconfig entry to depend on, not select PINCTRL_MSMJohn Stultz2020-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One fixup following my patch commit be117ca32261 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a selected config") being queued in LinusW's tree, as a new config entry was added for the msm8953 that also needs the change. Applies to LinusW's pinctrl devel tree. Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Prasad Sodagudi <psodagud@codeaurora.org> Cc: Vladimir Lypak <junak.pub@gmail.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201110215619.86076-1-john.stultz@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: sdx55: update kconfig dependencyVinod Koul2020-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit be117ca32261 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a dependency rather then a selected config") moved the qcom pinctrl drivers to have PINCTRL_MSM as dependency rather then a selected config, so do this change for SDX55 pinctrl driver as well. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201111043610.177168-1-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add SDX55 pincontrol driverJeevan Shriram2020-11-103-0/+1028
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial Qualcomm SDX55 pinctrl driver to support pin configuration with pinctrl framework for SDX55 SoC. [ported from downstream and tidy up] Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201109062620.14566-3-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Allow pinctrl-msm code to be loadable as a moduleJohn Stultz2020-11-102-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tweaks to allow pinctrl-msm code to be loadable as a module. This is needed in order to support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. This requires that we tweak Kconfigs selecting PINCTRL_MSM to also depend on QCOM_SCM || QCOM_SCM=n so that we match the module setting of QCOM_SCM. Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-2-john.stultz@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a ↵John Stultz2020-11-101-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | selected config This patch reworks PINCTRL_MSM to be a visible option, and instead of having the various SoC specific drivers select PINCTRL_MSM, this switches those configs to depend on PINCTRL_MSM. This is useful, as it will be needed in order to cleanly support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. Without this change, we would eventually have to add dependency lines to every config that selects PINCTRL_MSM, and that would becomes a maintenance headache. We also add PINCTRL_MSM to the arm64 defconfig to avoid surprises as otherwise PINCTRL_MSM/IPQ* options previously enabled, will be off. Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-1-john.stultz@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: add pinctrl driver for msm8953Vladimir Lypak2020-11-103-0/+1855
| | | | | | | | | | | | | | | | | | | | | | | | Add inititial pinctrl driver for MSM8953 platform. Compatible SoCs are: MSM8953, APQ8053, SDM(SDA)450, SDM(SDA)632. Based off CAF implementation. Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Vladimir Lypak <junak.pub@gmail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201007160611.942754-1-junak.pub@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: sm8250: Specify PDC mapBjorn Andersson2020-11-101-0/+18
| | | | | | | | | | | | | | | | | | | | Specify the PDC mapping for SM8250, so that gpio interrupts are propertly mapped to the wakeup IRQs of the PDC. Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201028043642.1141723-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callbackMaulik Shah2020-11-101-13/+19
|/ | | | | | | | | | | | | | | | | | | | | | | | | When GPIOs that are routed to PDC are used as output they can still latch the IRQ pending at GIC. As a result the spurious IRQ was handled when the client driver change the direction to input to starts using it as IRQ. Currently such erroneous latched IRQ are cleared with .irq_enable callback however if the driver continue to use GPIO as interrupt and invokes disable_irq() followed by enable_irq() then everytime during enable_irq() previously latched interrupt gets cleared. This can make edge IRQs not seen after enable_irq() if they had arrived after the driver has invoked disable_irq() and were pending at GIC. Move clearing erroneous IRQ to .irq_request_resources callback as this is the place where GPIO direction is changed as input and its locked as IRQ. While at this add a missing check to invoke msm_gpio_irq_clear_unmask() from .irq_enable callback only when GPIO is not routed to PDC. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1604561884-10166-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.10-1' of ↵Linus Torvalds2020-10-143-0/+640
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - NONE whatsoever, we don't even touch the core files this time around. New drivers: - New driver for the Toshiba Visconti SoC. - New subdriver for the Qualcomm MSM8226 SoC. - New subdriver for the Actions Semiconductor S500 SoC. - New subdriver for the Mediatek MT8192 SoC. - New subdriver for the Microchip SAMA7G5 SoC. Driver enhancements: - Intel Cherryview and Baytrail cleanups and refactorings. - Enhanced support for the Renesas R8A7790, more pins and groups. - Some optimizations for the MCP23S08 MCP23x17 variant. - Some cleanups around the Actions Semiconductor subdrivers. - A bunch of cleanups around the SH-PFC and Emma Mobile drivers. - The "SH-PFC" (literally SuperH pin function controller, I think) subdirectory is now renamed to the more neutral "renesas", as these are not very much centered around SuperH anymore. - Non-critical fixes for the Aspeed driver. - Non-critical fixes for the Ingenic (MIPS!) driver. - Fix a bunch of missing pins on the AMD pinctrl driver" * tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits) pinctrl: amd: Add missing pins to the pin group list dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI pinctrl: mediatek: Free eint data on failure pinctrl: single: fix debug output when #pinctrl-cells = 2 pinctrl: single: fix pinctrl_spec.args_count bounds check pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent pinctrl: cannonlake: Modify COMMUNITY macros to be consistent pinctrl: tigerlake: Fix register offsets for TGL-H variant pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2 pinctrl: mediatek: use devm_platform_ioremap_resource_byname() pinctrl: nuvoton: npcm7xx: Constify static ops structs pinctrl: mediatek: mt7622: add antsel pins/groups pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register() pinctrl: at91-pio4: add support for sama7g5 SoC dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5 pinctrl: spear: simplify the return expression of tvc_connect() pinctrl: spear: simplify the return expression of spear310_pinctrl_probe pinctrl: sprd: use module_platform_driver to simplify the code pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs. ...
| * pinctrl: qcom: Add msm8226 pinctrl driver.Bartosz Dudziak2020-08-273-0/+640
| | | | | | | | | | | | | | | | | | | | | | | | Add initial Qualcomm msm8226 pinctrl driver to support pin configuration with pinctrl framework for msm8226 SoC. - Initial formatting and style was taken from the msm8x74 pinctrl driver added by Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'irq-core-2020-10-12' of ↵Linus Torvalds2020-10-121-5/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "Updates for the interrupt subsystem: Core: - Allow trimming of interrupt hierarchy to support odd hardware setups where only a subset of the interrupts requires the full hierarchy. - Allow the retrigger mechanism to follow a hierarchy to simplify driver code. - Provide a mechanism to force enable wakeup interrrupts on suspend. - More infrastructure to handle IPIs in the core code Architectures: - Convert ARM/ARM64 IPI handling to utilize the interrupt core code. Drivers: - The usual pile of new interrupt chips (MStar, Actions Owl, TI PRUSS, Designware ICTL) - ARM(64) IPI related conversions - Wakeup support for Qualcom PDC - Prevent hierarchy corruption in the NVIDIA Tegra driver - The usual small fixes, improvements and cleanups all over the place" * tag 'irq-core-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits) dt-bindings: interrupt-controller: Add MStar interrupt controller irqchip/irq-mst: Add MStar interrupt controller support soc/tegra: pmc: Don't create fake interrupt hierarchy levels soc/tegra: pmc: Allow optional irq parent callbacks gpio: tegra186: Allow optional irq parent callbacks genirq/irqdomain: Allow partial trimming of irq_data hierarchy irqchip/qcom-pdc: Reset PDC interrupts during init irqchip/qcom-pdc: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag genirq/PM: Introduce IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag pinctrl: qcom: Use return value from irq_set_wake() call pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags ARM: Handle no IPI being registered in show_ipi_list() MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller irqchip: Add Actions Semi Owl SIRQ controller dt-bindings: interrupt-controller: Add Actions SIRQ controller binding dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller irqchip/dw-apb-ictl: Add primary interrupt controller support irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains genirq: Add stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER ...
| * | pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flagMaulik Shah2020-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the wakeirqs during suspend entry. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-5-git-send-email-mkshah@codeaurora.org
| * | pinctrl: qcom: Use return value from irq_set_wake() callMaulik Shah2020-10-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | msmgpio irqchip was not using return value of irq_set_irq_wake() callback since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor it implemented .irq_set_wake callback. This lead to irq_set_irq_wake() return error -ENXIO. However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE flag. Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent() instead of always returning success. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org
| * | pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flagsMaulik Shah2020-10-061-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked during suspend or during setting irq type since genirq checks irqchip flag of msmgpio irqchip which forwards these calls to its parent PDC irqchip. Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during suspend and mask before setting irq type. Masking before changing type make sures any spurious interrupt is not detected during this operation. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org
* | pinctrl: qcom: sm8250: correct sdc2_clkDmitry Baryshkov2020-10-011-1/+1
|/ | | | | | | | | | | | Correct sdc2_clk pin definition (register offset is wrong, verified by the msm-4.19 driver). Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200914091846.55204-1-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.9-1' of ↵Linus Torvalds2020-08-097-7/+29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of the pin control changes for the v5.9 kernel series: Core changes: - The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range() macro" was put in an immutable branch and merged into the pinctrl tree as well. We see these changes also here. - Improved debug output for pins used as GPIO. New drivers: - Ocelot Sparx5 SoC driver. - Intel Emmitsburg SoC subdriver. - Intel Tiger Lake-H SoC subdriver. - Qualcomm PM660 SoC subdriver. - Renesas SH-PFC R8A774E1 subdriver. Driver improvements: - Linear improvement and cleanups of the Intel drivers for Cherryview, Lynxpoint, Baytrail etc. Improved locking among other things. - Renesas SH-PFC has added support for RPC pins, groups, and functions to r8a77970 and r8a77980. - The newere Freescale (now NXP) i.MX8 pin controllers have been modularized. This is driven by the Google Android GKI initiative I think. - Open drain support for pins on the Qualcomm IPQ4019. - The Ingenic driver can handle both edges IRQ detection. - A big slew of documentation fixes all over the place. - A few irqchip template conversions by yours truly. * tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits) dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC pinctrl: stmfx: Use irqchip template pinctrl: amd: Use irqchip template pinctrl: mediatek: fix build for tristate changes pinctrl: samsung: Use bank name as irqchip name pinctrl: core: print gpio in pins debugfs file pinctrl: mediatek: add mt6779 eint support pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API pinctrl: mcp23s08: Use irqchip template pinctrl: sx150x: Use irqchip template dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes pinctrl: intel: Add Intel Emmitsburg pin controller support pinctl: ti: iodelay: Replace HTTP links with HTTPS ones Revert "gpio: omap: handle pin config bias flags" pinctrl: single: Use fallthrough pseudo-keyword pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword pinctrl: baytrail: Use fallthrough pseudo-keyword ...
| * pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-07-202-3/+3
| | | | | | | | | | | | | | | | | | | | | | Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200716212213.GA17623@embeddedor Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: pinctrl-msm8976: Remove unused variable 'nav_tsync_groups'Lee Jones2020-07-161-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following W=1 kernel build warning(s): drivers/pinctrl/qcom/pinctrl-msm8976.c:802:27: warning: ‘nav_tsync_groups’ defined but not used [-Wunused-const-variable=] 802 | static const char const nav_tsync_groups[] = { | ^~~~~~~~~~~~~~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Del Regno <kholk11@gmail.com> Cc: linux-arm-msm@vger.kernel.org Link: https://lore.kernel.org/r/20200713144930.1034632-10-lee.jones@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: pinctrl-msm: Complete 'struct msm_pinctrl' documentationLee Jones2020-07-161-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing descriptions for attributes and fix 1 formatting issue. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'desc' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'irq_chip' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'intr_target_use_scm' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'soc' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'phys_base' not described in 'msm_pinctrl' Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: linux-arm-msm@vger.kernel.org Link: https://lore.kernel.org/r/20200713144930.1034632-6-lee.jones@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: ipq4019: add open drain supportJaiganesh Narayanan2020-07-163-0/+16
| | | | | | | | | | | | | | | | | | | | [ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based WiFi APs. ] Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lore.kernel.org/r/20200703080646.23233-1-computersforpeace@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: ipq8074: route gpio interrupts to APPSKathiravan T2020-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | set target proc as APPS to route the gpio interrupts to APPS Co-developed-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org> Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1594107588-17055-1-git-send-email-kathirav@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-gpio: Add pm660(l) compatibilityKonrad Dybcio2020-07-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | Add support for pm660(l) SPMI GPIOs. The PMICs feature 13 and 12 GPIOs respectively, though with a lot of holes inbetween. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200622192558.152828-2-konradybcio@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'pinctrl-v5.8-4' of ↵Linus Torvalds2020-08-014-2/+79
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fix from Linus Walleij: "A single last minute pin control fix to the Qualcomm driver fixing missing dual edge PCH interrupts" * tag 'pinctrl-v5.8-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180
| * | pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180Douglas Anderson2020-07-164-2/+79
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on how you look at it, you can either say that: a) There is a PDC hardware issue (with the specific IP rev that exists on sc7180) that causes the PDC not to work properly when configured to handle dual edges. b) The dual edge feature of the PDC hardware was only added in later HW revisions and thus isn't in all hardware. Regardless of how you look at it, let's work around the lack of dual edge support by only ever letting our parent see requests for single edge interrupts on affected hardware. NOTE: it's possible that a driver requesting a dual edge interrupt might get several edges coalesced into a single IRQ. For instance if a line starts low and then goes high and low again, the driver that requested the IRQ is not guaranteed to be called twice. However, it is guaranteed that once the driver's interrupt handler starts running its first instruction that any new edges coming in will cause the interrupt to fire again. This is relatively commonplace for dual-edge gpio interrupts (many gpio controllers require software to emulate dual edge with single edge) so client drivers should be setup to handle it. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200714080254.v3.1.Ie0d730120b232a86a4eac1e2909bcbec844d1766@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: ipq6018 Add missing pins in qpic pin groupSivaprakash Murugesan2020-06-201-1/+2
| | | | | | | | | | | | | | | | | | | | The patch adds missing qpic data pins to qpic pingroup. These pins are necessary for the qpic nand to work. Fixes: ef1ea54eab0e ("pinctrl: qcom: Add ipq6018 pinctrl driver") Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592541089-17700-1-git-send-email-sivaprak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: spmi-gpio: fix warning about irq chip reusageDmitry Baryshkov2020-06-161-11/+10
|/ | | | | | | | | | | | | | | Fix the following warnings caused by reusage of the same irq_chip instance for all spmi-gpio gpio_irq_chip instances. Instead embed irq_chip into pmic_gpio_state struct. gpio gpiochip2: (c440000.qcom,spmi:pmic@2:gpio@c000): detected irqchip that is shared with multiple gpiochips: please fix the driver. gpio gpiochip3: (c440000.qcom,spmi:pmic@4:gpio@c000): detected irqchip that is shared with multiple gpiochips: please fix the driver. gpio gpiochip4: (c440000.qcom,spmi:pmic@a:gpio@c000): detected irqchip that is shared with multiple gpiochips: please fix the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200604002817.667160-1-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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