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* linux/kconfig.h: replace IF_ENABLED() with PTR_IF() in <linux/kernel.h>Masahiro Yamada2021-05-091-0/+3
| | | | | | | | | | | | | | | | | | | <linux/kconfig.h> is included from all the kernel-space source files, including C, assembly, linker scripts. It is intended to contain a minimal set of macros to evaluate CONFIG options. IF_ENABLED() is an intruder here because (x ? y : z) is C code, which should not be included from assembly files or linker scripts. Also, <linux/kconfig.h> is no longer self-contained because NULL is defined in <linux/stddef.h>. Move IF_ENABLED() out to <linux/kernel.h> as PTR_IF(). PTF_IF() takes the general boolean expression instead of a CONFIG option so that it fits better in <linux/kernel.h>. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org>
* Merge tag 'pinctrl-v5.13-1' of ↵Linus Torvalds2021-04-3086-1012/+9710
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is a lot going on! Core changes: - A semantic change to handle pinmux and pinconf in explicit order while up until now we depended on the semantic order in the device tree. The device tree is a functional programming language and does not imply any order, so the right thing is for the pin control core to provide these semantics. - Add a new pinmux-select debugfs file which makes it possible to go in and select functions for a pin manually (iteratively, at the prompt) for debugging purposes. - Fixes to gpio regmap handling for a new pin control driver making use of regmap-gpio. - Use octal permissions on debugfs files. New drivers: - A massive rewrite of the former custom pin control driver for MIPS Broadcom devices to instead use the pin control subsystem. New pin control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368, BCM63268 and BCM6318 SoC variants are implemented. - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are supported. - Support for the Rockchip RK3568/RK3566 pin controller. - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000. - Support for Mediatek MTK8195. - Add a new Xilinx ZynqMP pin control driver. Driver improvements and non-urgent fixes: - Modularization and improvements of the Rockchip drivers. - Some new pins added to the description of new Renesas SoCs. - Clarifications of the GPIO base calculation in the Intel driver. - Fix the function names for the MPP54 and MPP55 pins in the Armada CP110 pin controller. - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350. - Support for ACPI probing of the Qualcomm SC8180x. - Fix interrupt clear status on rockchip - Fix some missing pins on the Ingenic JZ4770, some semantic fixes for the behaviour of the Ingenic pin controller. Add DMIC pins for JZ4780, X1000, X1500 and X1830. - A slew of janitorial like of_node_put() calls" * tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: Add Xilinx ZynqMP pinctrl driver support firmware: xilinx: Add pinctrl support pinctrl: rockchip: do coding style for mux route struct pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param pinctrl: Introduce MODE group in enum pin_config_param pinctrl: Keep enum pin_config_param ordered by name dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver pinctrl: core: Fix kernel doc string for pin_get_name() pinctrl: mediatek: use spin lock in mtk_rmw pinctrl: add drive for I2C related pins on MT8195 pinctrl: add pinctrl driver on mt8195 dt-bindings: pinctrl: mt8195: add pinctrl file and binding document pinctrl: Ingenic: Add pinctrl driver for X2000. pinctrl: Ingenic: Add pinctrl driver for JZ4775. pinctrl: Ingenic: Add pinctrl driver for JZ4755. pinctrl: Ingenic: Add pinctrl driver for JZ4750. pinctrl: Ingenic: Add pinctrl driver for JZ4730. dt-bindings: pinctrl: Add bindings for new Ingenic SoCs. pinctrl: Ingenic: Reformat the code. pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs. ...
| * pinctrl: Add Xilinx ZynqMP pinctrl driver supportSai Krishna Potthuri2021-04-223-0/+921
| | | | | | | | | | | | | | | | | | | | Adding pinctrl driver for Xilinx ZynqMP platform. This driver queries pin information from firmware and registers pin control accordingly. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1619080202-31924-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: do coding style for mux route structJianqun Xu2021-04-221-570/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mux route tables take many lines for each SoC, and it will be more instances for newly SoC, that makes the file size increase larger. This patch only do coding style for mux route struct, by adding a new definition and replace the structs by script which supplied by huangtao@rock-chips.com sed -i -e " /static struct rockchip_mux_route_data /bcheck b :append-next-line N :check /^[^;]*$/bappend-next-line s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g s/\t{\n//g s/\t}, {\n//g s/\t},//g s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2), \1\n/g s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2), \1\n/g " drivers/pinctrl/pinctrl-rockchip.c Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210420091240.1246429-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Introduce MODE group in enum pin_config_paramAndy Shevchenko2021-04-225-12/+12
| | | | | | | | | | | | | | | | | | | | Better to have a MODE group of settings to keep them together when ordered alphabetically. Hence, rename PIN_CONFIG_LOW_POWER_MODE to PIN_CONFIG_MODE_LOW_POWER. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210412140741.39946-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: core: Fix kernel doc string for pin_get_name()Andy Shevchenko2021-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The kernel doc string mistakenly advertises the pin_get_name_from_id(). Fix it, otherwise kernel doc validator is not happy: .../core.c:168: warning: expecting prototype for pin_get_name_from_id(). Prototype was for pin_get_name() instead Fixes: dcb5dbc305b9 ("pinctrl: show pin name for pingroups in sysfs") Cc: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210415123521.86894-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: use spin lock in mtk_rmwTzung-Bi Shih2021-04-224-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 42a46434e9b1 ("pinctrl: add lock in mtk_rmw function.") uses mutex lock in mtk_rmw. However the function is possible called from atomic context. For example call trace: mutex_lock+0x28/0x64 mtk_rmw+0x38/0x80 [snip] max98357a_daiops_trigger+0x8c/0x9c soc_pcm_trigger+0x5c/0x10c The max98357a_daiops_trigger() could run in either atomic or non-atomic context. As a result, dmesg shows some similar messages: "BUG: sleeping function called from invalid context at kernel/locking/mutex.c:254". Uses spin lock in mtk_rmw instead. Fixes: 42a46434e9b1 ("pinctrl: add lock in mtk_rmw function.") Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20210419093449.3125704-1-tzungbi@google.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add drive for I2C related pins on MT8195Zhiyong Tao2021-04-223-0/+41
| | | | | | | | | | | | | | | | | | | | This patch provides the advanced drive raw data setting version for I2C used pins on MT8195. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20210413055702.27535-4-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add pinctrl driver on mt8195Zhiyong Tao2021-04-224-0/+2504
| | | | | | | | | | | | | | | | | | This commit includes pinctrl driver for mt8195. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20210413055702.27535-3-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add pinctrl driver for X2000.周琰杰 (Zhou Yanjie)2021-04-221-13/+579
| | | | | | | | | | | | | | | | | | | | | | Add support for probing the pinctrl-ingenic driver on the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-13-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add pinctrl driver for JZ4775.周琰杰 (Zhou Yanjie)2021-04-221-0/+279
| | | | | | | | | | | | | | | | | | | | | | Add support for probing the pinctrl-ingenic driver on the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-12-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add pinctrl driver for JZ4755.周琰杰 (Zhou Yanjie)2021-04-221-0/+139
| | | | | | | | | | | | | | | | | | | | | | Add support for probing the pinctrl-ingenic driver on the JZ4755 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-11-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add pinctrl driver for JZ4750.周琰杰 (Zhou Yanjie)2021-04-221-0/+142
| | | | | | | | | | | | | | | | | | | | | | Add support for probing the pinctrl-ingenic driver on the JZ4750 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-10-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add pinctrl driver for JZ4730.周琰杰 (Zhou Yanjie)2021-04-221-16/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for probing the pinctrl-ingenic driver on the JZ4730 SoC from Ingenic. This driver is derived from Paul Boddie. It is worth to noting that the JZ4730 SoC is special in having two control registers (upper/lower), so add code to handle the JZ4730 specific register offsets and some register pairs which have 2 bits for each GPIO pin. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> # on Letux400 Co-developed-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-9-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Reformat the code.周琰杰 (Zhou Yanjie)2021-04-221-36/+35
| | | | | | | | | | | | | | | | | | | | | | 1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section. 2.Add tabs before values to align the code in the macro definition section. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-7-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.周琰杰 (Zhou Yanjie)2021-04-221-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | 1.Add DMIC pins support for the JZ4780 SoC. 2.Add DMIC pins support for the X1000 SoC. 3.Add DMIC pins support for the X1500 SoC. 4.Add DMIC pins support for the X1830 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-6-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Improve LCD pins related code.周琰杰 (Zhou Yanjie)2021-04-221-49/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.In the JZ4740 part, remove pointless "lcd-no-pins", use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft". Currently, in the mainline, no other devicetree out there is using the "lcd-18bit-tft" ABI, so we should be able to replace it safely. 2.In the JZ4725B part, adjust the location of the LCD pins related code to keep them consistent with the style of other parts. 3.In the JZ4760 part, add the missing comma and adjust element order in "jz4760_lcd_special_pins[]", keep them in the order of CLS/SPL/PS/REV like other "lcd_special_pins" arrays. And adjust the location of the "jz4760_lcd_generic" related code to keep them consistent with the style of other parts. 4.In the JZ4770 part, remove pointless "lcd-no-pins", add the missing "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic". 5.In the X1000 part and the X1500 part, remove pointless "lcd-no-pins". 6.In the X1830 part, replace "lcd-rgb-18bit" with "lcd-tft-8bit" and "lcd-tft-24bit", because of the description of the TRANS_CONFIG.MODE register bits in the PM manual of the X1830, shows that the X1830 only supppots 24bit mode and 8bit mode for tft interface, only 18 pins in the GPIO table are because of the data[17:16], the data[9:8], and the data[1:0] has not been connected. And according to the description, the two interfaces supported by X1830 are respectively referred to as "TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced with "lcd-tft-xxx" to avoid confusion. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups.周琰杰 (Zhou Yanjie)2021-04-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | Adjust the sequence of X1830's SSI related codes to make it consistent with other Ingenic SoCs. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add support for read the pin configuration of X1830.周琰杰 (Zhou Yanjie)2021-04-221-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | Add X1830 support in "ingenic_pinconf_get()", so that it can read the configuration of X1830 SoC correctly. Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.") Cc: <stable@vger.kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.周琰杰 (Zhou Yanjie)2021-04-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The MII group of JZ4770's MAC should have 7 pins, add missing pins to the MII group. Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.") Cc: <stable@vger.kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-2-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIBJulian Braha2021-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When PINCTRL_MSM is enabled, and GPIOLIB is disabled, Kbuild gives the following warning: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_MSM [=y] && PINCTRL [=y] && (ARCH_QCOM || COMPILE_TEST [=y]) This is because PINCTRL_MSM selects GPIOLIB_IRQCHIP, without selecting or depending on GPIOLIB, despite GPIOLIB_IRQCHIP depending on GPIOLIB. Having PINCTRL_MSM select GPIOLIB will cause a recursive dependency error. Signed-off-by: Julian Braha <julianbraha@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210414025138.480085-1-julianbraha@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: at91-pio4: Fix slew rate disablementTudor Ambarus2021-04-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The slew rate was enabled by default for each configuration of the pin. In case the pin had more than one configuration, even if we set the slew rate as disabled in the device tree, the next pin configuration would set again the slew rate enabled by default, overwriting the slew rate disablement. Instead of enabling the slew rate by default for each pin configuration, enable the slew rate by default just once per pin, regardless of the number of configurations. This way the slew rate disablement will also work for cases where pins have multiple configurations. Fixes: c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: samsung: use 'int' for register masks in ExynosKrzysztof Kozlowski2021-04-101-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Special Function Registers on all Exynos SoC, including ARM64, are 32-bit wide, so entire driver uses matching functions like readl() or writel(). On 64-bit ARM using unsigned long for register masks: 1. makes little sense as immediately after bitwise operation it will be cast to 32-bit value when calling writel(), 2. is actually error-prone because it might promote other operands to 64-bit. Addresses-Coverity: Unintentional integer overflow Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20210408195029.69974-1-krzysztof.kozlowski@canonical.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom-pmic-gpio: Add support for pm8008Guru Das Srinagesh2021-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | Add support for the two GPIOs present on Qualcomm Technologies, Inc. PM8008. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org> Link: https://lore.kernel.org/r/129d241ee510e28536d35dbfeee75474e12d8d22.1617901945.git.gurus@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: Disallow driver unbindFabio Estevam2021-04-0815-0/+15
| | | | | | | | | | | | | | | | | | | | Performing the 'unbind' operation on pinctrl drivers is not a sensible usecase, so pass the suppress_bind_attrs atribute to prevent it. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210328183034.555702-2-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: Remove unneeded of_match_ptr()Fabio Estevam2021-04-0815-15/+15
| | | | | | | | | | | | | | | | | | | | | | i.MX is a DT-only platform, so of_match_ptr() can be safely removed. Remove the unneeded of_match_ptr(). Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210328183034.555702-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: ti: fix error return code of ti_iodelay_dt_node_to_map()Junlin Yang2021-04-081-1/+3
| | | | | | | | | | | | | | | | | | when devm_kcalloc fails, use -ENOMEM instead of -EINVAL, and consistent with other devm_kcalloc return values. Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210330062655.1027-1-angkery@163.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: add support for rk3568Jianqun Xu2021-04-081-2/+290
| | | | | | | | | | | | | | | | | | RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports set iomux, pull, drive strength and schmitt. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210319081441.368358-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: Print invalid AF warning inside stm32_pctrl_is_function_valid()Marek Vasut2021-04-081-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "invalid function %d on pin %d .\n" message is triplicated in the driver in different variants, just pull it into the function and have it once in the driver. The bonus is that all variants of the message now print the pin number and AF consistently, so it is easier to debug such pinmux problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabien Dessenne <fabien.dessenne@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210406180035.279249-1-marex@denx.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: bcm63xx: Fix More dependenciesRandy Dunlap2021-04-081-1/+6
| | | | | | | | | | | | | | | | | | | | The additional patch below fixes all of the kconfig warnings and build errors for me. Link: https://lore.kernel.org/r/9e1cec76-1c0a-9203-7995-4c2d09b711d8@infradead.org Signed-off-by: Randy Dunlap <rdunlap@infradead.org> [Tweaked some other line in the BCMxxx] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'renesas-pinctrl-for-v5.13-tag2' of ↵Linus Walleij2021-04-0719-202/+497
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 (take two) - Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, - Miscellaneous cleanups and improvements.
| | * pinctrl: renesas: r8a7791: Add bias pinconf supportGeert Uytterhoeven2021-03-241-16/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, using the common R-Car bias handling. Note that on RZ/G1 SoCs, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-7-geert+renesas@glider.be
| | * pinctrl: renesas: Add support for R-Car SoCs with pull-down only pinsGeert Uytterhoeven2021-03-242-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the common R-Car bias handling supports pin controllers with either: 1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers, for controlling both pin pull-up and pin pull-down, 2. A single pin Pull-Up control register (PUPR), for controlling pin pull-up. Add support for a variant of #2, where some bits in the single pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up. This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W, M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C. To describe such a register, SoC-specific drivers need to provide two instances of pinmux_bias_reg: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-6-geert+renesas@glider.be
| | * pinctrl: renesas: Add PORT_GP_CFG_7 macrosGeert Uytterhoeven2021-03-241-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add PORT_GP_CFG_7() and PORT_GP_7() helper macros, to be used by the r8a7791 subdriver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-5-geert+renesas@glider.be
| | * pinctrl: renesas: Factor out common R-Mobile bias handlingGeert Uytterhoeven2021-03-245-126/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin control sub-drivers for SH/R-Mobile SoCs contain almost identical bias handling. The only SoC-specific part is the mapping from pin numbers to PORTnCR registers. Reduce code duplication by factoring out the bias handling to the common pinctrl.c code. Use a callback to handle the pin/register mapping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-4-geert+renesas@glider.be
| | * pinctrl: renesas: Move R-Car bias helpers to sh_pfc.hGeert Uytterhoeven2021-03-2413-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Renesas Pin Function Controller driver uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Hence move the R-Car bias helper declarations from core.h to sh_pfc.h, and drop the inclusion of core.h from SoC-specific drivers that no longer need it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-3-geert+renesas@glider.be
| | * pinctrl: renesas: Make sh_pfc_pin_to_bias_reg() staticGeert Uytterhoeven2021-03-243-26/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now all R-Car pin control drivers have been converted to the common R-Car bias handling, sh_pfc_pin_to_bias_reg() is only called from a single place. Move it from core.c to pinctrl.c, make it static, and rename it to rcar_pin_to_bias_reg(), as it is specific to R-Car SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-2-geert+renesas@glider.be
| * | pinctrl: bcm63xx: Fix dependenciesLinus Walleij2021-03-311-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add depends on OF so we don't get weird build errors on randconfig. Also order selects the same as the other drivers for pure aestetic reasons. Reported-by: Randy Dunlap <rdunlap@infradead.org> Cc: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: bcm6362: fix warningÁlvaro Fernández Rojas2021-03-311-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of bcm6362_set_gpio() produces the following warning on x86_64: drivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio': drivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 503 | (uint32_t) desc->drv_data, 0); | ^ Modify the code to make it similar to bcm63268_set_gpio() in order to fix the warning. Fixes: 705791e23ecd ("pinctrl: add a pincontrol driver for BCM6362") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.com Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge branch 'ib-bcm63xx' into develLinus Walleij2021-03-3010-0/+3268
| |\ \
| | * | pinctrl: add a pincontrol driver for BCM6318Álvaro Fernández Rojas2021-03-293-0/+507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs to different functions. BCM6318 is similar to BCM6328 with the addition of a pad register, and the GPIO meaning of the mux register changes based on the GPIO number. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-23-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: add a pincontrol driver for BCM63268Álvaro Fernández Rojas2021-03-293-0/+652
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs to different functions. Depending on the mux, these are either single pin configurations or whole pin groups. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-20-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: add a pincontrol driver for BCM6368Álvaro Fernández Rojas2021-03-293-0/+532
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 GPIOs onto alternative functions. Not all are documented. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-17-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: add a pincontrol driver for BCM6362Álvaro Fernández Rojas2021-03-293-0/+626
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual GPIO pins to the LED controller, to be available by the integrated wifi, or other functions. It also supports overlay groups, of which only NAND is documented. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-14-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: add a pincontrol driver for BCM6358Álvaro Fernández Rojas2021-03-293-0/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different functions onto the GPIO pins. It does not support configuring individual pins but only whole groups. These groups may overlap, and still require the directions to be set correctly in the GPIO register. In addition the functions register controls other, not directly mux related functions. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-11-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: add a pincontrol driver for BCM6328Álvaro Fernández Rojas2021-03-293-0/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as GPIOs, as LEDs for the integrated LED controller, or various other functions. Its pincontrol mux registers also control other aspects, like switching the second USB port between host and device mode. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-8-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: bcm: add bcm63xx base codeÁlvaro Fernández Rojas2021-03-294-0/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper for registering BCM63XX pin controllers. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-5-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'intel-pinctrl-v5.13-1' of ↵Linus Walleij2021-03-301-3/+4
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
| | * | | pinctrl: intel: No need to disable IRQs in the handlerAndy Shevchenko2021-03-251-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * | | | drivers: pinctrl: Remove duplicate include of io.hWan Jiabing2021-03-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | linux/io.h has been included at line 6, so remove the duplicate include at line 18. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210323013727.135571-1-wanjiabing@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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