From 25c1a2466008a75955e80df3cc0698410a0cec72 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 24 Dec 2011 10:52:19 +0900 Subject: rtc-s3c: add variants for S3C2443 and S3C2416 Especially the TICNT registers are different from the two rtc types that currently exists. Signed-off-by: Heiko Stuebner Acked-by: Alessandro Zummo Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/include/plat/regs-rtc.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h index a7d944f4131e..0f8263e93eea 100644 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h @@ -22,11 +22,28 @@ #define S3C2410_RTCCON_RTCEN (1 << 0) #define S3C2410_RTCCON_CNTSEL (1 << 2) #define S3C2410_RTCCON_CLKRST (1 << 3) +#define S3C2443_RTCCON_TICSEL (1 << 4) #define S3C64XX_RTCCON_TICEN (1 << 8) #define S3C2410_TICNT S3C2410_RTCREG(0x44) #define S3C2410_TICNT_ENABLE (1 << 7) +/* S3C2443: tick count is 15 bit wide + * TICNT[6:0] contains upper 7 bits + * TICNT1[7:0] contains lower 8 bits + */ +#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) +#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) +#define S3C2443_TICNT1_PART(x) (x & 0xff) + +/* S3C2416: tick count is 32 bit wide + * TICNT[6:0] contains bits [14:8] + * TICNT1[7:0] contains lower 8 bits + * TICNT2[16:0] contains upper 17 bits + */ +#define S3C2416_TICNT2 S3C2410_RTCREG(0x48) +#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) + #define S3C2410_RTCALM S3C2410_RTCREG(0x50) #define S3C2410_RTCALM_ALMEN (1 << 6) #define S3C2410_RTCALM_YEAREN (1 << 5) -- cgit v1.2.1