From 7e94984495dbce182260fa3dd15687439236b0a1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 6 May 2013 15:11:10 -0600 Subject: clk: tegra: remove USB from clk init table The USB clocks are just clock gates, so no need to set a specific clock. In fact trying to set a specific clock is just a NOP if the requested clockrate is the same as those of the parent (clk_m) or will trigger a WARN_ON() if rates don't match up. As we are not setting a specific rate, nor activating the clocks at init, there is no point in keeping the the usb entries in the clock init table. Signed-off-by: Lucas Stach Acked-by: Peter De Schrijver Reviewed-by: Prashant Gaikwad Acked-by: Mike Turquette Tested-by: Stephen Warren Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- drivers/clk/tegra/clk-tegra20.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/clk/tegra/clk-tegra20.c') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 8292a00c3de9..d80c7cc23581 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1234,9 +1234,6 @@ static __initdata struct tegra_clk_init_table init_table[] = { {uartc, pll_p, 0, 0}, {uartd, pll_p, 0, 0}, {uarte, pll_p, 0, 0}, - {usbd, clk_max, 12000000, 0}, - {usb2, clk_max, 12000000, 0}, - {usb3, clk_max, 12000000, 0}, {pll_a, clk_max, 56448000, 1}, {pll_a_out0, clk_max, 11289600, 1}, {cdev1, clk_max, 0, 1}, -- cgit v1.2.1 From 6ec3240047ee6a4b34f90d45e19ed179bc9b4a2e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 6 May 2013 15:11:11 -0600 Subject: clk: tegra: add ac97 controller clock AC97 controller clock is hardwired to pll_a_out0. Signed-off-by: Lucas Stach Acked-by: Peter De Schrijver Reviewed-by: Prashant Gaikwad Acked-by: Mike Turquette Tested-by: Stephen Warren Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- drivers/clk/tegra/clk-tegra20.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/clk/tegra/clk-tegra20.c') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index d80c7cc23581..075db0c99edb 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void) struct clk *clk; int i; + /* ac97 */ + clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", + TEGRA_PERIPH_ON_APB, + clk_base, 0, 3, &periph_l_regs, + periph_clk_enb_refcnt); + clk_register_clkdev(clk, NULL, "tegra20-ac97"); + clks[ac97] = clk; + /* apbdma */ clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 0, 34, &periph_h_regs, -- cgit v1.2.1