From 79ef0abcd85842bc12ffb3297b958565f060464c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 1 Aug 2011 13:02:17 +0900 Subject: ASoC: Implement new DC servo readback mode for late WM8994 revisions Later WM8994 devices implement a new DC servo readback mode with the register used to access the offset moved to register 0x59. Implement support for this and enable it on the appropriate devices. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- include/linux/mfd/wm8994/registers.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index f3ee84284670..61529143db57 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -72,6 +72,7 @@ #define WM8994_DC_SERVO_2 0x55 #define WM8994_DC_SERVO_4 0x57 #define WM8994_DC_SERVO_READBACK 0x58 +#define WM8994_DC_SERVO_4E 0x59 #define WM8994_ANALOGUE_HP_1 0x60 #define WM8958_MIC_DETECT_1 0xD0 #define WM8958_MIC_DETECT_2 0xD1 -- cgit v1.2.1 From c18eee31812d42ecd0aa5c39d21d41c15b30eaab Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 10 Aug 2011 19:25:40 +0900 Subject: ASoC: Add bitfield definitions for WM8958 MICBIAS registers Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- include/linux/mfd/wm8994/registers.h | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index 61529143db57..64bf91e4dfa9 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -1921,6 +1921,44 @@ #define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ #define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ +/* + * R61 (0x3D) - MICBIAS1 + */ +#define WM8958_MICB1_RATE 0x0020 /* MICB1_RATE */ +#define WM8958_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ +#define WM8958_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ +#define WM8958_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ +#define WM8958_MICB1_MODE 0x0010 /* MICB1_MODE */ +#define WM8958_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */ +#define WM8958_MICB1_MODE_SHIFT 4 /* MICB1_MODE */ +#define WM8958_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ +#define WM8958_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */ +#define WM8958_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */ +#define WM8958_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */ +#define WM8958_MICB1_DISCH 0x0001 /* MICB1_DISCH */ +#define WM8958_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ +#define WM8958_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ +#define WM8958_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ + +/* + * R62 (0x3E) - MICBIAS2 + */ +#define WM8958_MICB2_RATE 0x0020 /* MICB2_RATE */ +#define WM8958_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ +#define WM8958_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ +#define WM8958_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ +#define WM8958_MICB2_MODE 0x0010 /* MICB2_MODE */ +#define WM8958_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */ +#define WM8958_MICB2_MODE_SHIFT 4 /* MICB2_MODE */ +#define WM8958_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ +#define WM8958_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */ +#define WM8958_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */ +#define WM8958_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */ +#define WM8958_MICB2_DISCH 0x0001 /* MICB2_DISCH */ +#define WM8958_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ +#define WM8958_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ +#define WM8958_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ + /* * R76 (0x4C) - Charge Pump (1) */ -- cgit v1.2.1 From 1ddc07d0f13a753f8e345e0538562e1899d2bc26 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 16 Aug 2011 10:08:48 +0900 Subject: ASoC: Add WM8958 noise gate support Signed-off-by: Mark Brown --- include/linux/mfd/wm8994/registers.h | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index 64bf91e4dfa9..83ecdcd8aaf9 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -134,6 +134,8 @@ #define WM8994_AIF1_DAC1_FILTERS_2 0x421 #define WM8994_AIF1_DAC2_FILTERS_1 0x422 #define WM8994_AIF1_DAC2_FILTERS_2 0x423 +#define WM8958_AIF1_DAC1_NOISE_GATE 0x430 +#define WM8958_AIF1_DAC2_NOISE_GATE 0x431 #define WM8994_AIF1_DRC1_1 0x440 #define WM8994_AIF1_DRC1_2 0x441 #define WM8994_AIF1_DRC1_3 0x442 @@ -191,6 +193,7 @@ #define WM8994_AIF2_ADC_FILTERS 0x510 #define WM8994_AIF2_DAC_FILTERS_1 0x520 #define WM8994_AIF2_DAC_FILTERS_2 0x521 +#define WM8958_AIF2_DAC_NOISE_GATE 0x530 #define WM8994_AIF2_DRC_1 0x540 #define WM8994_AIF2_DRC_2 0x541 #define WM8994_AIF2_DRC_3 0x542 @@ -2987,6 +2990,34 @@ #define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ #define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ +/* + * R1072 (0x430) - AIF1 DAC1 Noise Gate + */ +#define WM8958_AIF1DAC1_NG_HLD_MASK 0x0060 /* AIF1DAC1_NG_HLD - [6:5] */ +#define WM8958_AIF1DAC1_NG_HLD_SHIFT 5 /* AIF1DAC1_NG_HLD - [6:5] */ +#define WM8958_AIF1DAC1_NG_HLD_WIDTH 2 /* AIF1DAC1_NG_HLD - [6:5] */ +#define WM8958_AIF1DAC1_NG_THR_MASK 0x000E /* AIF1DAC1_NG_THR - [3:1] */ +#define WM8958_AIF1DAC1_NG_THR_SHIFT 1 /* AIF1DAC1_NG_THR - [3:1] */ +#define WM8958_AIF1DAC1_NG_THR_WIDTH 3 /* AIF1DAC1_NG_THR - [3:1] */ +#define WM8958_AIF1DAC1_NG_ENA 0x0001 /* AIF1DAC1_NG_ENA */ +#define WM8958_AIF1DAC1_NG_ENA_MASK 0x0001 /* AIF1DAC1_NG_ENA */ +#define WM8958_AIF1DAC1_NG_ENA_SHIFT 0 /* AIF1DAC1_NG_ENA */ +#define WM8958_AIF1DAC1_NG_ENA_WIDTH 1 /* AIF1DAC1_NG_ENA */ + +/* + * R1073 (0x431) - AIF1 DAC2 Noise Gate + */ +#define WM8958_AIF1DAC2_NG_HLD_MASK 0x0060 /* AIF1DAC2_NG_HLD - [6:5] */ +#define WM8958_AIF1DAC2_NG_HLD_SHIFT 5 /* AIF1DAC2_NG_HLD - [6:5] */ +#define WM8958_AIF1DAC2_NG_HLD_WIDTH 2 /* AIF1DAC2_NG_HLD - [6:5] */ +#define WM8958_AIF1DAC2_NG_THR_MASK 0x000E /* AIF1DAC2_NG_THR - [3:1] */ +#define WM8958_AIF1DAC2_NG_THR_SHIFT 1 /* AIF1DAC2_NG_THR - [3:1] */ +#define WM8958_AIF1DAC2_NG_THR_WIDTH 3 /* AIF1DAC2_NG_THR - [3:1] */ +#define WM8958_AIF1DAC2_NG_ENA 0x0001 /* AIF1DAC2_NG_ENA */ +#define WM8958_AIF1DAC2_NG_ENA_MASK 0x0001 /* AIF1DAC2_NG_ENA */ +#define WM8958_AIF1DAC2_NG_ENA_SHIFT 0 /* AIF1DAC2_NG_ENA */ +#define WM8958_AIF1DAC2_NG_ENA_WIDTH 1 /* AIF1DAC2_NG_ENA */ + /* * R1088 (0x440) - AIF1 DRC1 (1) */ @@ -3598,6 +3629,20 @@ #define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ #define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ +/* + * R1328 (0x530) - AIF2 DAC Noise Gate + */ +#define WM8958_AIF2DAC_NG_HLD_MASK 0x0060 /* AIF2DAC_NG_HLD - [6:5] */ +#define WM8958_AIF2DAC_NG_HLD_SHIFT 5 /* AIF2DAC_NG_HLD - [6:5] */ +#define WM8958_AIF2DAC_NG_HLD_WIDTH 2 /* AIF2DAC_NG_HLD - [6:5] */ +#define WM8958_AIF2DAC_NG_THR_MASK 0x000E /* AIF2DAC_NG_THR - [3:1] */ +#define WM8958_AIF2DAC_NG_THR_SHIFT 1 /* AIF2DAC_NG_THR - [3:1] */ +#define WM8958_AIF2DAC_NG_THR_WIDTH 3 /* AIF2DAC_NG_THR - [3:1] */ +#define WM8958_AIF2DAC_NG_ENA 0x0001 /* AIF2DAC_NG_ENA */ +#define WM8958_AIF2DAC_NG_ENA_MASK 0x0001 /* AIF2DAC_NG_ENA */ +#define WM8958_AIF2DAC_NG_ENA_SHIFT 0 /* AIF2DAC_NG_ENA */ +#define WM8958_AIF2DAC_NG_ENA_WIDTH 1 /* AIF2DAC_NG_ENA */ + /* * R1344 (0x540) - AIF2 DRC (1) */ -- cgit v1.2.1 From 1df5981b82d9eabdd6e66d1d9514164c02329345 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Jun 2011 19:28:10 +0100 Subject: mfd: Convert WM831x to use regmap API Factor out the register read/write code to use the register map API. We still need some wm831x specific code and locking in place to check that the user key is handled correctly but only on the write side, reads are not affected by the key. Signed-off-by: Mark Brown Acked-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 8dda8ded5cda..44acdb25681b 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -18,6 +18,7 @@ #include #include #include +#include /* * Register values. @@ -361,12 +362,8 @@ struct wm831x { struct mutex io_lock; struct device *dev; - int (*read_dev)(struct wm831x *wm831x, unsigned short reg, - int bytes, void *dest); - int (*write_dev)(struct wm831x *wm831x, unsigned short reg, - int bytes, void *src); - void *control_data; + struct regmap *regmap; int irq; /* Our chip IRQ */ struct mutex irq_lock; @@ -416,4 +413,6 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); void wm831x_auxadc_init(struct wm831x *wm831x); +extern struct regmap_config wm831x_regmap_config; + #endif -- cgit v1.2.1 From d6c645fc00777a6f8a7df1f580065ec30c71be7b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 17 Jun 2011 13:02:27 +0100 Subject: mfd: Convert WM8994 to use new register map API Signed-off-by: Mark Brown Acked-by: Samuel Ortiz --- include/linux/mfd/wm8994/core.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h index f0b69cdae41c..45df450d869f 100644 --- a/include/linux/mfd/wm8994/core.h +++ b/include/linux/mfd/wm8994/core.h @@ -24,6 +24,7 @@ enum wm8994_type { struct regulator_dev; struct regulator_bulk_data; +struct regmap; #define WM8994_NUM_GPIO_REGS 11 #define WM8994_NUM_LDO_REGS 2 @@ -50,18 +51,12 @@ struct regulator_bulk_data; #define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN) struct wm8994 { - struct mutex io_lock; struct mutex irq_lock; enum wm8994_type type; struct device *dev; - int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, - int bytes, void *dest); - int (*write_dev)(struct wm8994 *wm8994, unsigned short reg, - int bytes, const void *src); - - void *control_data; + struct regmap *regmap; int gpio_base; int irq_base; -- cgit v1.2.1 From 50eeef5d3cea5afcced17a0410e8b0bf88997845 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 9 Aug 2011 16:34:29 +0900 Subject: mfd: Convert WM8400 to regmap API Signed-off-by: Mark Brown --- include/linux/mfd/wm8400-private.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h index 2aab4e93a5c9..0147b6968510 100644 --- a/include/linux/mfd/wm8400-private.h +++ b/include/linux/mfd/wm8400-private.h @@ -25,16 +25,15 @@ #include #include +struct regmap; + #define WM8400_REGISTER_COUNT 0x55 struct wm8400 { struct device *dev; - int (*read_dev)(void *data, char reg, int count, u16 *dst); - int (*write_dev)(void *data, char reg, int count, const u16 *src); - struct mutex io_lock; - void *io_data; + struct regmap *regmap; u16 reg_cache[WM8400_REGISTER_COUNT]; -- cgit v1.2.1 From 500c524aad173864a58e128d0be9713fa5846471 Mon Sep 17 00:00:00 2001 From: Xin Xie Date: Tue, 9 Aug 2011 18:47:50 +0800 Subject: regulator: tps6586x: add SMx slew rate setting Add output vlotage slew rate setting for SM0/SM1 Signed-off-by: Xin Xie Signed-off-by: Danny Huang Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- include/linux/mfd/tps6586x.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index b6bab1b04e25..b19176eab44d 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -1,6 +1,18 @@ #ifndef __LINUX_MFD_TPS6586X_H #define __LINUX_MFD_TPS6586X_H +#define TPS6586X_SLEW_RATE_INSTANTLY 0x00 +#define TPS6586X_SLEW_RATE_110UV 0x01 +#define TPS6586X_SLEW_RATE_220UV 0x02 +#define TPS6586X_SLEW_RATE_440UV 0x03 +#define TPS6586X_SLEW_RATE_880UV 0x04 +#define TPS6586X_SLEW_RATE_1760UV 0x05 +#define TPS6586X_SLEW_RATE_3520UV 0x06 +#define TPS6586X_SLEW_RATE_7040UV 0x07 + +#define TPS6586X_SLEW_RATE_SET 0x08 +#define TPS6586X_SLEW_RATE_MASK 0x07 + enum { TPS6586X_ID_SM_0, TPS6586X_ID_SM_1, @@ -48,6 +60,10 @@ enum { TPS6586X_INT_RTC_ALM2, }; +struct tps6586x_settings { + int slew_rate; +}; + struct tps6586x_subdev_info { int id; const char *name; -- cgit v1.2.1 From a69882aec380512e5d6acff9bfc4336dc5162bb4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 15 Sep 2011 15:39:24 +0300 Subject: MFD: twl6040: Add accessor for revision ID For client driver to use, if they need chip resvision information. Signed-off-by: Peter Ujfalusi Acked-by: Samuel Ortiz Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 4c806f6d663e..cb3b82207120 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -225,4 +225,9 @@ unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); int twl6040_irq_init(struct twl6040 *twl6040); void twl6040_irq_exit(struct twl6040 *twl6040); +static inline int twl6040_get_revid(struct twl6040 *twl6040) +{ + return twl6040->rev; +} + #endif /* End of __TWL6040_CODEC_H__ */ -- cgit v1.2.1 From a52762eee97d42344691c190cf8786dd9edde4d7 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 15 Sep 2011 15:39:27 +0300 Subject: ASoC: twl6040: Chip initialization cleanup There is no need to write to the vio registers at probe time, since most them either read only, or shared with MFD or not used. On the other hand it is a good idea to updated the ASICREV register in the cache at this time. After power up we need to restore some registers. Clean up the list to contain only the registers we are going to restore. Signed-off-by: Peter Ujfalusi Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index cb3b82207120..ec1ec794fa23 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -70,9 +70,6 @@ #define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1) -#define TWL6040_VIOREGNUM 18 -#define TWL6040_VDDREGNUM 21 - /* INTID (0x03) fields */ #define TWL6040_THINT 0x01 -- cgit v1.2.1 From 523d9cfbb2094e095ff08a01c4eac10cc7d287c3 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 15 Sep 2011 18:54:53 +0200 Subject: mfd: Support software initiated shutdown of WM831x PMICs In systems where there is no hardware signal from the processor to the PMIC to initiate the final power off sequence we must initiate the shutdown with a register write to the PMIC. Support such systems in the driver. Since this may prevent a full shutdown of the system platform data is used to enable the feature. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 3 +++ include/linux/mfd/wm831x/pdata.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 44acdb25681b..ed8fe0d04097 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -371,6 +371,8 @@ struct wm831x { int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ + bool soft_shutdown; + /* Chip revision based flags */ unsigned has_gpio_ena:1; /* Has GPIO enable bit */ unsigned has_cs_sts:1; /* Has current sink status bit */ @@ -409,6 +411,7 @@ int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq); void wm831x_device_exit(struct wm831x *wm831x); int wm831x_device_suspend(struct wm831x *wm831x); +void wm831x_device_shutdown(struct wm831x *wm831x); int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); void wm831x_auxadc_init(struct wm831x *wm831x); diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h index 0ba24599fe51..1d7a3f7b3b5d 100644 --- a/include/linux/mfd/wm831x/pdata.h +++ b/include/linux/mfd/wm831x/pdata.h @@ -123,6 +123,9 @@ struct wm831x_pdata { /** Disable the touchscreen */ bool disable_touch; + /** The driver should initiate a power off sequence during shutdown */ + bool soft_shutdown; + int irq_base; int gpio_base; int gpio_defaults[WM831X_GPIO_NUM]; -- cgit v1.2.1 From d17bf31832d30b91225a84b53fae380dbdd07d3d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 22 Sep 2011 11:05:48 +0300 Subject: ASoC: twl6040: Introduce SW only shadow register Software only shadow register to be used by the driver. For example Earpiece path will need this shadow register. Signed-off-by: Peter Ujfalusi Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index ec1ec794fa23..47470cadf969 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -68,8 +68,6 @@ #define TWL6040_REG_ACCCTL 0x2D #define TWL6040_REG_STATUS 0x2E -#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1) - /* INTID (0x03) fields */ #define TWL6040_THINT 0x01 -- cgit v1.2.1 From ab6cf13943303f865320407b17b0f86095d23ce3 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 22 Sep 2011 11:05:54 +0300 Subject: ASoC/MFD: twl6040: Combine bit definitions for Headset control registers Use one set of defines for the HS bits, since they are identical in both control register. Signed-off-by: Peter Ujfalusi Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 47470cadf969..d9e05eabef33 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -120,15 +120,10 @@ #define TWL6040_LPLLFIN 0x08 #define TWL6040_HPLLSEL 0x10 -/* HSLCTL (0x10) fields */ +/* HSLCTL/R (0x10/0x11) fields */ -#define TWL6040_HSDACMODEL 0x02 -#define TWL6040_HSDRVMODEL 0x08 - -/* HSRCTL (0x11) fields */ - -#define TWL6040_HSDACMODER 0x02 -#define TWL6040_HSDRVMODER 0x08 +#define TWL6040_HSDACMODE (1 << 1) +#define TWL6040_HSDRVMODE (1 << 3) /* VIBCTLL (0x18) fields */ -- cgit v1.2.1 From b1f43bf3a52b085b786adf0b719712df574955f9 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 24 May 2011 17:35:40 +0800 Subject: mfd: Add WM1811 support The WM1811 is mostly register compatible with the WM8994 and WM8958, providing a high performance audio hub CODEC in a small form factor suitable for ultra compact system designs. Signed-off-by: Mark Brown Acked-by: Samuel Ortiz --- include/linux/mfd/wm8994/core.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h index f0b69cdae41c..bfb221b3abf7 100644 --- a/include/linux/mfd/wm8994/core.h +++ b/include/linux/mfd/wm8994/core.h @@ -20,6 +20,7 @@ enum wm8994_type { WM8994 = 0, WM8958 = 1, + WM1811 = 2, }; struct regulator_dev; -- cgit v1.2.1 From 81204c84ca46604a04ab3d43ccfa1e464e6b1303 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 24 May 2011 17:35:53 +0800 Subject: ASoC: Add WM1811 support The WM1811 is mostly register compatible with the WM8994 and WM8958, providing a high performance audio hub CODEC in a small form factor suitable for ultra compact system designs. Signed-off-by: Mark Brown --- include/linux/mfd/wm8994/registers.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index 83ecdcd8aaf9..fae295048a8b 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -2069,6 +2069,10 @@ /* * R96 (0x60) - Analogue HP (1) */ +#define WM1811_HPOUT1_ATTN 0x0100 /* HPOUT1_ATTN */ +#define WM1811_HPOUT1_ATTN_MASK 0x0100 /* HPOUT1_ATTN */ +#define WM1811_HPOUT1_ATTN_SHIFT 8 /* HPOUT1_ATTN */ +#define WM1811_HPOUT1_ATTN_WIDTH 1 /* HPOUT1_ATTN */ #define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ #define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ -- cgit v1.2.1 From 1e036f65329901a2432c92132b785654944743d9 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 12 Oct 2011 11:57:53 +0300 Subject: Input: twl6040: Simplify vibra regsiter definitions The bits within the two control registers (for left and right channel) are identical. Use common names for the bits acros the two register. Also add the missing definition for the path selection bit. Signed-off-by: Peter Ujfalusi Acked-by: Dmitry Torokhov Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index d9e05eabef33..e6c755db4560 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -125,24 +125,18 @@ #define TWL6040_HSDACMODE (1 << 1) #define TWL6040_HSDRVMODE (1 << 3) -/* VIBCTLL (0x18) fields */ +/* VIBCTLL/R (0x18/0x1A) fields */ -#define TWL6040_VIBENAL 0x01 -#define TWL6040_VIBCTRLL 0x04 -#define TWL6040_VIBCTRLLP 0x08 -#define TWL6040_VIBCTRLLN 0x10 +#define TWL6040_VIBENA (1 << 0) +#define TWL6040_VIBSEL (1 << 1) +#define TWL6040_VIBCTRL (1 << 2) +#define TWL6040_VIBCTRL_P (1 << 3) +#define TWL6040_VIBCTRL_N (1 << 4) -/* VIBDATL (0x19) fields */ +/* VIBDATL/R (0x19/0x1B) fields */ #define TWL6040_VIBDAT_MAX 0x64 -/* VIBCTLR (0x1A) fields */ - -#define TWL6040_VIBENAR 0x01 -#define TWL6040_VIBCTRLR 0x04 -#define TWL6040_VIBCTRLRP 0x08 -#define TWL6040_VIBCTRLRN 0x10 - /* GPOCTL (0x1E) fields */ #define TWL6040_GPO1 0x01 -- cgit v1.2.1 From 31b402e3c9eb839a00530511dcf7de47bbf723f6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 12 Oct 2011 11:57:54 +0300 Subject: MFD: twl6040: Cache the vibra control registers The vibra control register will be used from the ASoC codec driver as well. In order to avoid latency issues caused by I2C read access, cache the two control register within the core driver, so we do not need to reach out to the chip to read it back. Signed-off-by: Peter Ujfalusi Acked-by: Samuel Ortiz Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index e6c755db4560..2f8585a4c74b 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -184,6 +184,7 @@ struct twl6040 { int audpwron; int power_count; int rev; + u8 vibra_ctrl_cache[2]; int pll; unsigned int sysclk; -- cgit v1.2.1 From 70601ec10a2450369d554e49d708ab26deb17b66 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 12 Oct 2011 11:57:55 +0300 Subject: MFD: twl6040: function to query the vibra status for clients If the client only interested, if any of the vibra channels enabled, or if any of the channels are set to receive audio data via PDM. This function targets mainly the vibra driver, so it can check if it is allowed to execute effects ot not. Signed-off-by: Peter Ujfalusi Acked-by: Samuel Ortiz Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 2f8585a4c74b..87a4778ed4b0 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -209,10 +209,13 @@ int twl6040_get_pll(struct twl6040 *twl6040); unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); int twl6040_irq_init(struct twl6040 *twl6040); void twl6040_irq_exit(struct twl6040 *twl6040); +/* Get the combined status of the vibra control register */ +int twl6040_get_vibralr_status(struct twl6040 *twl6040); static inline int twl6040_get_revid(struct twl6040 *twl6040) { return twl6040->rev; } + #endif /* End of __TWL6040_CODEC_H__ */ -- cgit v1.2.1 From 33b6816ca3a4027a1b5444c83c1c24c0b1991262 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 12 Oct 2011 14:46:02 +0300 Subject: ASoC: twl6040: Workaround for headset DC offset caused pop noise Both Headset DAC need to be turned on/off at the same time before any of the output drivers are enabled (HS Left/Right, Earpiece). Move the HS DAC enable code to sequenced DAPM_SUPPLY, and attach it to the DACs. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- include/linux/mfd/twl6040.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 87a4778ed4b0..2463c2619596 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -122,6 +122,7 @@ /* HSLCTL/R (0x10/0x11) fields */ +#define TWL6040_HSDACENA (1 << 0) #define TWL6040_HSDACMODE (1 << 1) #define TWL6040_HSDRVMODE (1 << 3) -- cgit v1.2.1 From 6e3ad118041f56db752a5eb2b557517d14592af7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 8 Aug 2011 17:04:40 +0900 Subject: mfd: Convert pcf50633 to use new register map API Signed-off-by: Mark Brown Tested-by: Lars-Peter Clausen Signed-off-by: Samuel Ortiz --- include/linux/mfd/pcf50633/core.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h index 50d4a047118d..a80840752b4c 100644 --- a/include/linux/mfd/pcf50633/core.h +++ b/include/linux/mfd/pcf50633/core.h @@ -21,6 +21,7 @@ #include struct pcf50633; +struct regmap; #define PCF50633_NUM_REGULATORS 11 @@ -134,7 +135,7 @@ enum { struct pcf50633 { struct device *dev; - struct i2c_client *i2c_client; + struct regmap *regmap; struct pcf50633_platform_data *pdata; int irq; -- cgit v1.2.1 From bd4a40b57b13907b4fe01b6c605be56d8f3733fe Mon Sep 17 00:00:00 2001 From: Karl Komierowski Date: Wed, 10 Aug 2011 15:09:43 +0200 Subject: mfd: Refactor ab8500 GPADC API, add raw access Refactor the GPADC interface to avoid bugs in calling code: - ab8500_gpadc_[convert|read_raw|ad_to_voltage] clarifies each functions use case, *convert wraps *read_raw, and we can access raw ADC values properly. - Renamed gpadc function arguments from "input" to "channel" to clarify use, so we don't get confused again. Signed-off-by: Kalle Komierowski Reviewed-by: Mattias Wallin Reviewed-by: John Beckett Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/ab8500/gpadc.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/ab8500/gpadc.h b/include/linux/mfd/ab8500/gpadc.h index 46b954011f16..252966769d93 100644 --- a/include/linux/mfd/ab8500/gpadc.h +++ b/include/linux/mfd/ab8500/gpadc.h @@ -27,6 +27,9 @@ struct ab8500_gpadc; struct ab8500_gpadc *ab8500_gpadc_get(char *name); -int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 input); +int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel); +int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel); +int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, + u8 channel, int ad_value); #endif /* _AB8500_GPADC_H */ -- cgit v1.2.1 From 881de67046f424fc3a6e05b1c681c12afd94e802 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 22 Aug 2011 15:43:55 +0200 Subject: mfd: Allow WM8994 LDO enable pulls to be disabled In systems where the LDO enables are always driven (for example, being connected to an always on supply rail or a GPIO which is driven by the CPU even in suspend) then we can disable the pull downs on the LDO for a small power savings. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm8994/core.h | 2 ++ include/linux/mfd/wm8994/pdata.h | 7 +++++++ 2 files changed, 9 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h index f0b69cdae41c..5ab71bd76f9c 100644 --- a/include/linux/mfd/wm8994/core.h +++ b/include/linux/mfd/wm8994/core.h @@ -63,6 +63,8 @@ struct wm8994 { void *control_data; + bool ldo_ena_always_driven; + int gpio_base; int irq_base; diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index 97cf4f27d647..ea32f306dca6 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -167,6 +167,13 @@ struct wm8994_pdata { /* WM8958 microphone bias configuration */ int micbias[2]; + + /* Disable the internal pull downs on the LDOs if they are + * always driven (eg, connected to an always on supply or + * GPIO that always drives an output. If they float power + * consumption will rise. + */ + bool ldo_ena_always_driven; }; #endif -- cgit v1.2.1 From 01fdaab8ffced1deeee14d9c7d2745f37349484e Mon Sep 17 00:00:00 2001 From: MyungJoo Ham Date: Fri, 19 Aug 2011 14:39:40 +0900 Subject: mfd: Wake-up from Suspend MAX8997 support - Support wake-up from suspend-to-ram. - Handle pending interrupt after a resume. - If pdata->wakeup is enabled, by default, the device is assumed to be capable of wakeup (the interrupt pin is connected to a wakeup-source GPIO) and may wakeup the system (MAX8997 has a power button input pin). Signed-off-by: MyungJoo Ham Signed-off-by: Kyungmin Park Signed-off-by: Samuel Ortiz --- include/linux/mfd/max8997-private.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h index 5ff2400ad46c..3f4deb62d6b0 100644 --- a/include/linux/mfd/max8997-private.h +++ b/include/linux/mfd/max8997-private.h @@ -326,7 +326,6 @@ struct max8997_dev { int irq; int ono; int irq_base; - bool wakeup; struct mutex irqlock; int irq_masks_cur[MAX8997_IRQ_GROUP_NR]; int irq_masks_cache[MAX8997_IRQ_GROUP_NR]; -- cgit v1.2.1 From fec316d63219f610e5385f5e54e6c3ea459e58e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 24 Aug 2011 15:28:21 +0200 Subject: mfd: Provide a generic version of mc13xxx adc_do_conversion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is needed to convert the touch driver away from using struct mc13783. Note this patch drops MC13783_ADC0_ADREFMODE. This is unused and doesn't exist on mc13892. Signed-off-by: Uwe Kleine-König Signed-off-by: Samuel Ortiz --- include/linux/mfd/mc13783.h | 35 ++++++++++++++++++----------------- include/linux/mfd/mc13xxx.h | 19 +++++++++++++++++++ 2 files changed, 37 insertions(+), 17 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h index 7d0f3d6a0002..e7a3c0169f63 100644 --- a/include/linux/mfd/mc13783.h +++ b/include/linux/mfd/mc13783.h @@ -89,18 +89,15 @@ static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq) return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq); } -#define MC13783_ADC0 43 -#define MC13783_ADC0_ADREFEN (1 << 10) -#define MC13783_ADC0_ADREFMODE (1 << 11) -#define MC13783_ADC0_TSMOD0 (1 << 12) -#define MC13783_ADC0_TSMOD1 (1 << 13) -#define MC13783_ADC0_TSMOD2 (1 << 14) -#define MC13783_ADC0_ADINC1 (1 << 16) -#define MC13783_ADC0_ADINC2 (1 << 17) - -#define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 | \ - MC13783_ADC0_TSMOD1 | \ - MC13783_ADC0_TSMOD2) +#define MC13783_ADC0 MC13XXX_ADC0 +#define MC13783_ADC0_ADREFEN MC13XXX_ADC0_ADREFEN +#define MC13783_ADC0_TSMOD0 MC13XXX_ADC0_TSMOD0 +#define MC13783_ADC0_TSMOD1 MC13XXX_ADC0_TSMOD1 +#define MC13783_ADC0_TSMOD2 MC13XXX_ADC0_TSMOD2 +#define MC13783_ADC0_ADINC1 MC13XXX_ADC0_ADINC1 +#define MC13783_ADC0_ADINC2 MC13XXX_ADC0_ADINC2 + +#define MC13783_ADC0_TSMOD_MASK MC13XXX_ADC0_TSMOD_MASK #define mc13783_regulator_init_data mc13xxx_regulator_init_data #define mc13783_regulator_platform_data mc13xxx_regulator_platform_data @@ -115,12 +112,16 @@ static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq) #define MC13783_USE_REGULATOR MC13XXX_USE_REGULATOR #define MC13783_USE_LED MC13XXX_USE_LED -#define MC13783_ADC_MODE_TS 1 -#define MC13783_ADC_MODE_SINGLE_CHAN 2 -#define MC13783_ADC_MODE_MULT_CHAN 3 +#define MC13783_ADC_MODE_TS MC13XXX_ADC_MODE_TS +#define MC13783_ADC_MODE_SINGLE_CHAN MC13XXX_ADC_MODE_SINGLE_CHAN +#define MC13783_ADC_MODE_MULT_CHAN MC13XXX_ADC_MODE_MULT_CHAN -int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, - unsigned int channel, unsigned int *sample); +static inline int mc13783_adc_do_conversion(struct mc13783 *mc13783, + unsigned int mode, unsigned int channel, unsigned int *sample) +{ + return mc13xxx_adc_do_conversion(mc13783_to_mc13xxx(mc13783), mode, + channel, sample); +} #define MC13783_REG_SW1A 0 diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index c064beaaccb7..6e7c0ac36d09 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -37,6 +37,9 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq); int mc13xxx_get_flags(struct mc13xxx *mc13xxx); +int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, + unsigned int mode, unsigned int channel, unsigned int *sample); + #define MC13XXX_IRQ_ADCDONE 0 #define MC13XXX_IRQ_ADCBISDONE 1 #define MC13XXX_IRQ_TS 2 @@ -150,4 +153,20 @@ struct mc13xxx_platform_data { struct mc13xxx_leds_platform_data *leds; }; +#define MC13XXX_ADC_MODE_TS 1 +#define MC13XXX_ADC_MODE_SINGLE_CHAN 2 +#define MC13XXX_ADC_MODE_MULT_CHAN 3 + +#define MC13XXX_ADC0 43 +#define MC13XXX_ADC0_ADREFEN (1 << 10) +#define MC13XXX_ADC0_TSMOD0 (1 << 12) +#define MC13XXX_ADC0_TSMOD1 (1 << 13) +#define MC13XXX_ADC0_TSMOD2 (1 << 14) +#define MC13XXX_ADC0_ADINC1 (1 << 16) +#define MC13XXX_ADC0_ADINC2 (1 << 17) + +#define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \ + MC13XXX_ADC0_TSMOD1 | \ + MC13XXX_ADC0_TSMOD2) + #endif /* ifndef __LINUX_MFD_MC13XXX_H */ -- cgit v1.2.1 From b46880e57b4c513adeb2608c3700b352860b5662 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 24 Aug 2011 15:28:25 +0200 Subject: mfd: Remove mc13783 API functions and symbols MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that all in-tree users are fixed to use the more general mc13xxx API the obsolete stuff can go away. Signed-off-by: Uwe Kleine-König Signed-off-by: Samuel Ortiz --- include/linux/mfd/mc13783.h | 112 -------------------------------------------- 1 file changed, 112 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h index e7a3c0169f63..a8eeda773a7b 100644 --- a/include/linux/mfd/mc13783.h +++ b/include/linux/mfd/mc13783.h @@ -12,118 +12,6 @@ #include -struct mc13783; - -struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783); - -static inline void mc13783_lock(struct mc13783 *mc13783) -{ - mc13xxx_lock(mc13783_to_mc13xxx(mc13783)); -} - -static inline void mc13783_unlock(struct mc13783 *mc13783) -{ - mc13xxx_unlock(mc13783_to_mc13xxx(mc13783)); -} - -static inline int mc13783_reg_read(struct mc13783 *mc13783, - unsigned int offset, u32 *val) -{ - return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val); -} - -static inline int mc13783_reg_write(struct mc13783 *mc13783, - unsigned int offset, u32 val) -{ - return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val); -} - -static inline int mc13783_reg_rmw(struct mc13783 *mc13783, - unsigned int offset, u32 mask, u32 val) -{ - return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val); -} - -static inline int mc13783_get_flags(struct mc13783 *mc13783) -{ - return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783)); -} - -static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq, - irq_handler_t handler, const char *name, void *dev) -{ - return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq, - handler, name, dev); -} - -static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq, - irq_handler_t handler, const char *name, void *dev) -{ - return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq, - handler, name, dev); -} - -static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev) -{ - return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev); -} - -static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq) -{ - return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq); -} - -static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq) -{ - return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq); -} -static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq, - int *enabled, int *pending) -{ - return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783), - irq, enabled, pending); -} - -static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq) -{ - return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq); -} - -#define MC13783_ADC0 MC13XXX_ADC0 -#define MC13783_ADC0_ADREFEN MC13XXX_ADC0_ADREFEN -#define MC13783_ADC0_TSMOD0 MC13XXX_ADC0_TSMOD0 -#define MC13783_ADC0_TSMOD1 MC13XXX_ADC0_TSMOD1 -#define MC13783_ADC0_TSMOD2 MC13XXX_ADC0_TSMOD2 -#define MC13783_ADC0_ADINC1 MC13XXX_ADC0_ADINC1 -#define MC13783_ADC0_ADINC2 MC13XXX_ADC0_ADINC2 - -#define MC13783_ADC0_TSMOD_MASK MC13XXX_ADC0_TSMOD_MASK - -#define mc13783_regulator_init_data mc13xxx_regulator_init_data -#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data -#define mc13783_led_platform_data mc13xxx_led_platform_data -#define mc13783_leds_platform_data mc13xxx_leds_platform_data - -#define mc13783_platform_data mc13xxx_platform_data -#define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN -#define MC13783_USE_CODEC MC13XXX_USE_CODEC -#define MC13783_USE_ADC MC13XXX_USE_ADC -#define MC13783_USE_RTC MC13XXX_USE_RTC -#define MC13783_USE_REGULATOR MC13XXX_USE_REGULATOR -#define MC13783_USE_LED MC13XXX_USE_LED - -#define MC13783_ADC_MODE_TS MC13XXX_ADC_MODE_TS -#define MC13783_ADC_MODE_SINGLE_CHAN MC13XXX_ADC_MODE_SINGLE_CHAN -#define MC13783_ADC_MODE_MULT_CHAN MC13XXX_ADC_MODE_MULT_CHAN - -static inline int mc13783_adc_do_conversion(struct mc13783 *mc13783, - unsigned int mode, unsigned int channel, unsigned int *sample) -{ - return mc13xxx_adc_do_conversion(mc13783_to_mc13xxx(mc13783), mode, - channel, sample); -} - - #define MC13783_REG_SW1A 0 #define MC13783_REG_SW1B 1 #define MC13783_REG_SW2A 2 -- cgit v1.2.1 From 5da721c87aee3d94cfc48384073c2ec51a0b9a3b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 15 Sep 2011 18:54:53 +0200 Subject: mfd: Support software initiated shutdown of WM831x PMICs In systems where there is no hardware signal from the processor to the PMIC to initiate the final power off sequence we must initiate the shutdown with a register write to the PMIC. Support such systems in the driver. Since this may prevent a full shutdown of the system platform data is used to enable the feature. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 3 +++ include/linux/mfd/wm831x/pdata.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 8dda8ded5cda..fb3e84f92e90 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -374,6 +374,8 @@ struct wm831x { int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ + bool soft_shutdown; + /* Chip revision based flags */ unsigned has_gpio_ena:1; /* Has GPIO enable bit */ unsigned has_cs_sts:1; /* Has current sink status bit */ @@ -412,6 +414,7 @@ int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq); void wm831x_device_exit(struct wm831x *wm831x); int wm831x_device_suspend(struct wm831x *wm831x); +void wm831x_device_shutdown(struct wm831x *wm831x); int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); void wm831x_auxadc_init(struct wm831x *wm831x); diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h index 0ba24599fe51..1d7a3f7b3b5d 100644 --- a/include/linux/mfd/wm831x/pdata.h +++ b/include/linux/mfd/wm831x/pdata.h @@ -123,6 +123,9 @@ struct wm831x_pdata { /** Disable the touchscreen */ bool disable_touch; + /** The driver should initiate a power off sequence during shutdown */ + bool soft_shutdown; + int irq_base; int gpio_base; int gpio_defaults[WM831X_GPIO_NUM]; -- cgit v1.2.1 From 5ab9059d7f2055f434140046e74d3d811e4cbb15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20R=C3=A9tornaz?= Date: Sun, 18 Sep 2011 17:57:35 +0200 Subject: mfd: Remove unused mc13xxx defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Rétornaz Signed-off-by: Uwe Kleine-König Signed-off-by: Samuel Ortiz --- include/linux/mfd/mc13xxx.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index 6e7c0ac36d09..1acf9cbf5f25 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -145,8 +145,6 @@ struct mc13xxx_platform_data { #define MC13XXX_USE_CODEC (1 << 1) #define MC13XXX_USE_ADC (1 << 2) #define MC13XXX_USE_RTC (1 << 3) -#define MC13XXX_USE_REGULATOR (1 << 4) -#define MC13XXX_USE_LED (1 << 5) unsigned int flags; struct mc13xxx_regulator_platform_data regulators; -- cgit v1.2.1 From 30fc7ac3f62945a714d9842edae313a757efb49d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20R=C3=A9tornaz?= Date: Sun, 18 Sep 2011 18:10:53 +0200 Subject: input: Add power button support for mc13783 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds support for the power-on buttons of MC13783 PMIC. Signed-off-by: Philippe Rétornaz Acked-by: Dmitry Torokhov Signed-off-by: Uwe Kleine-König Signed-off-by: Samuel Ortiz --- include/linux/mfd/mc13xxx.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index 1acf9cbf5f25..3816c2fac0ad 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -140,6 +140,22 @@ struct mc13xxx_leds_platform_data { char tc3_period; }; +struct mc13xxx_buttons_platform_data { +#define MC13783_BUTTON_DBNC_0MS 0 +#define MC13783_BUTTON_DBNC_30MS 1 +#define MC13783_BUTTON_DBNC_150MS 2 +#define MC13783_BUTTON_DBNC_750MS 3 +#define MC13783_BUTTON_ENABLE (1 << 2) +#define MC13783_BUTTON_POL_INVERT (1 << 3) +#define MC13783_BUTTON_RESET_EN (1 << 4) + int b1on_flags; + unsigned short b1on_key; + int b2on_flags; + unsigned short b2on_key; + int b3on_flags; + unsigned short b3on_key; +}; + struct mc13xxx_platform_data { #define MC13XXX_USE_TOUCHSCREEN (1 << 0) #define MC13XXX_USE_CODEC (1 << 1) @@ -149,6 +165,7 @@ struct mc13xxx_platform_data { struct mc13xxx_regulator_platform_data regulators; struct mc13xxx_leds_platform_data *leds; + struct mc13xxx_buttons_platform_data *buttons; }; #define MC13XXX_ADC_MODE_TS 1 -- cgit v1.2.1 From 7583a213ec3bde3082547ee37ad96214513bc1cb Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 16 Sep 2011 13:21:47 +0100 Subject: mfd: Simulate active high IRQs with wm831x In order to ease system integration provide a simulation of active high IRQs on the GPIOs by polling the GPIO status when an IRQ is generated. This isn't ideal on several fronts and will miss initially active IRQs in the current implementation but it should work well for most cases. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index fb3e84f92e90..272f7fb5f8b8 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -385,6 +385,7 @@ struct wm831x { /* Used by the interrupt controller code to post writes */ int gpio_update[WM831X_NUM_GPIO_REGS]; + bool gpio_level[WM831X_NUM_GPIO_REGS]; struct mutex auxadc_lock; struct list_head auxadc_pending; -- cgit v1.2.1 From 1f5a371c075a7101fe75a75cde5aad928460a42e Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Wed, 21 Sep 2011 13:03:07 +0200 Subject: mfd: Add Intel MSIC driver Add support for Intel MSIC chip found on Intel Medfield platforms. This chip embeds several subdevices: audio, ADC, GPIO, power button, etc. The driver creates platform device for each subdevice. We also provide an MSIC register access API which should replace the more generic SCU IPC interface currently used. Existing drivers can choose whether they convert to this new API or stick with the SCU IPC interface. Signed-off-by: Mika Westerberg Signed-off-by: Samuel Ortiz --- include/linux/mfd/intel_msic.h | 456 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 456 insertions(+) create mode 100644 include/linux/mfd/intel_msic.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/intel_msic.h b/include/linux/mfd/intel_msic.h new file mode 100644 index 000000000000..439a7a617bc9 --- /dev/null +++ b/include/linux/mfd/intel_msic.h @@ -0,0 +1,456 @@ +/* + * include/linux/mfd/intel_msic.h - Core interface for Intel MSIC + * + * Copyright (C) 2011, Intel Corporation + * Author: Mika Westerberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_INTEL_MSIC_H__ +#define __LINUX_MFD_INTEL_MSIC_H__ + +/* ID */ +#define INTEL_MSIC_ID0 0x000 /* RO */ +#define INTEL_MSIC_ID1 0x001 /* RO */ + +/* IRQ */ +#define INTEL_MSIC_IRQLVL1 0x002 +#define INTEL_MSIC_ADC1INT 0x003 +#define INTEL_MSIC_CCINT 0x004 +#define INTEL_MSIC_PWRSRCINT 0x005 +#define INTEL_MSIC_PWRSRCINT1 0x006 +#define INTEL_MSIC_CHRINT 0x007 +#define INTEL_MSIC_CHRINT1 0x008 +#define INTEL_MSIC_RTCIRQ 0x009 +#define INTEL_MSIC_GPIO0LVIRQ 0x00a +#define INTEL_MSIC_GPIO1LVIRQ 0x00b +#define INTEL_MSIC_GPIOHVIRQ 0x00c +#define INTEL_MSIC_VRINT 0x00d +#define INTEL_MSIC_OCAUDIO 0x00e +#define INTEL_MSIC_ACCDET 0x00f +#define INTEL_MSIC_RESETIRQ1 0x010 +#define INTEL_MSIC_RESETIRQ2 0x011 +#define INTEL_MSIC_MADC1INT 0x012 +#define INTEL_MSIC_MCCINT 0x013 +#define INTEL_MSIC_MPWRSRCINT 0x014 +#define INTEL_MSIC_MPWRSRCINT1 0x015 +#define INTEL_MSIC_MCHRINT 0x016 +#define INTEL_MSIC_MCHRINT1 0x017 +#define INTEL_MSIC_RTCIRQMASK 0x018 +#define INTEL_MSIC_GPIO0LVIRQMASK 0x019 +#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a +#define INTEL_MSIC_GPIOHVIRQMASK 0x01b +#define INTEL_MSIC_VRINTMASK 0x01c +#define INTEL_MSIC_OCAUDIOMASK 0x01d +#define INTEL_MSIC_ACCDETMASK 0x01e +#define INTEL_MSIC_RESETIRQ1MASK 0x01f +#define INTEL_MSIC_RESETIRQ2MASK 0x020 +#define INTEL_MSIC_IRQLVL1MSK 0x021 +#define INTEL_MSIC_PBCONFIG 0x03e +#define INTEL_MSIC_PBSTATUS 0x03f /* RO */ + +/* GPIO */ +#define INTEL_MSIC_GPIO0LV7CTLO 0x040 +#define INTEL_MSIC_GPIO0LV6CTLO 0x041 +#define INTEL_MSIC_GPIO0LV5CTLO 0x042 +#define INTEL_MSIC_GPIO0LV4CTLO 0x043 +#define INTEL_MSIC_GPIO0LV3CTLO 0x044 +#define INTEL_MSIC_GPIO0LV2CTLO 0x045 +#define INTEL_MSIC_GPIO0LV1CTLO 0x046 +#define INTEL_MSIC_GPIO0LV0CTLO 0x047 +#define INTEL_MSIC_GPIO1LV7CTLOS 0x048 +#define INTEL_MSIC_GPIO1LV6CTLO 0x049 +#define INTEL_MSIC_GPIO1LV5CTLO 0x04a +#define INTEL_MSIC_GPIO1LV4CTLO 0x04b +#define INTEL_MSIC_GPIO1LV3CTLO 0x04c +#define INTEL_MSIC_GPIO1LV2CTLO 0x04d +#define INTEL_MSIC_GPIO1LV1CTLO 0x04e +#define INTEL_MSIC_GPIO1LV0CTLO 0x04f +#define INTEL_MSIC_GPIO0LV7CTLI 0x050 +#define INTEL_MSIC_GPIO0LV6CTLI 0x051 +#define INTEL_MSIC_GPIO0LV5CTLI 0x052 +#define INTEL_MSIC_GPIO0LV4CTLI 0x053 +#define INTEL_MSIC_GPIO0LV3CTLI 0x054 +#define INTEL_MSIC_GPIO0LV2CTLI 0x055 +#define INTEL_MSIC_GPIO0LV1CTLI 0x056 +#define INTEL_MSIC_GPIO0LV0CTLI 0x057 +#define INTEL_MSIC_GPIO1LV7CTLIS 0x058 +#define INTEL_MSIC_GPIO1LV6CTLI 0x059 +#define INTEL_MSIC_GPIO1LV5CTLI 0x05a +#define INTEL_MSIC_GPIO1LV4CTLI 0x05b +#define INTEL_MSIC_GPIO1LV3CTLI 0x05c +#define INTEL_MSIC_GPIO1LV2CTLI 0x05d +#define INTEL_MSIC_GPIO1LV1CTLI 0x05e +#define INTEL_MSIC_GPIO1LV0CTLI 0x05f +#define INTEL_MSIC_PWM0CLKDIV1 0x061 +#define INTEL_MSIC_PWM0CLKDIV0 0x062 +#define INTEL_MSIC_PWM1CLKDIV1 0x063 +#define INTEL_MSIC_PWM1CLKDIV0 0x064 +#define INTEL_MSIC_PWM2CLKDIV1 0x065 +#define INTEL_MSIC_PWM2CLKDIV0 0x066 +#define INTEL_MSIC_PWM0DUTYCYCLE 0x067 +#define INTEL_MSIC_PWM1DUTYCYCLE 0x068 +#define INTEL_MSIC_PWM2DUTYCYCLE 0x069 +#define INTEL_MSIC_GPIO0HV3CTLO 0x06d +#define INTEL_MSIC_GPIO0HV2CTLO 0x06e +#define INTEL_MSIC_GPIO0HV1CTLO 0x06f +#define INTEL_MSIC_GPIO0HV0CTLO 0x070 +#define INTEL_MSIC_GPIO1HV3CTLO 0x071 +#define INTEL_MSIC_GPIO1HV2CTLO 0x072 +#define INTEL_MSIC_GPIO1HV1CTLO 0x073 +#define INTEL_MSIC_GPIO1HV0CTLO 0x074 +#define INTEL_MSIC_GPIO0HV3CTLI 0x075 +#define INTEL_MSIC_GPIO0HV2CTLI 0x076 +#define INTEL_MSIC_GPIO0HV1CTLI 0x077 +#define INTEL_MSIC_GPIO0HV0CTLI 0x078 +#define INTEL_MSIC_GPIO1HV3CTLI 0x079 +#define INTEL_MSIC_GPIO1HV2CTLI 0x07a +#define INTEL_MSIC_GPIO1HV1CTLI 0x07b +#define INTEL_MSIC_GPIO1HV0CTLI 0x07c + +/* SVID */ +#define INTEL_MSIC_SVIDCTRL0 0x080 +#define INTEL_MSIC_SVIDCTRL1 0x081 +#define INTEL_MSIC_SVIDCTRL2 0x082 +#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */ +#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */ +#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */ +#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */ +#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087 +#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088 +#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089 +#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a +#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b +#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c +#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */ +#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */ +#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */ +#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */ +#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */ +#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */ +#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */ +#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */ + +/* VREG */ +#define INTEL_MSIC_VCCLATCH 0x0c0 +#define INTEL_MSIC_VNNLATCH 0x0c1 +#define INTEL_MSIC_VCCCNT 0x0c2 +#define INTEL_MSIC_SMPSRAMP 0x0c3 +#define INTEL_MSIC_VNNCNT 0x0c4 +#define INTEL_MSIC_VNNAONCNT 0x0c5 +#define INTEL_MSIC_VCC122AONCNT 0x0c6 +#define INTEL_MSIC_V180AONCNT 0x0c7 +#define INTEL_MSIC_V500CNT 0x0c8 +#define INTEL_MSIC_VIHFCNT 0x0c9 +#define INTEL_MSIC_LDORAMP1 0x0ca +#define INTEL_MSIC_LDORAMP2 0x0cb +#define INTEL_MSIC_VCC108AONCNT 0x0cc +#define INTEL_MSIC_VCC108ASCNT 0x0cd +#define INTEL_MSIC_VCC108CNT 0x0ce +#define INTEL_MSIC_VCCA100ASCNT 0x0cf +#define INTEL_MSIC_VCCA100CNT 0x0d0 +#define INTEL_MSIC_VCC180AONCNT 0x0d1 +#define INTEL_MSIC_VCC180CNT 0x0d2 +#define INTEL_MSIC_VCC330CNT 0x0d3 +#define INTEL_MSIC_VUSB330CNT 0x0d4 +#define INTEL_MSIC_VCCSDIOCNT 0x0d5 +#define INTEL_MSIC_VPROG1CNT 0x0d6 +#define INTEL_MSIC_VPROG2CNT 0x0d7 +#define INTEL_MSIC_VEMMCSCNT 0x0d8 +#define INTEL_MSIC_VEMMC1CNT 0x0d9 +#define INTEL_MSIC_VEMMC2CNT 0x0da +#define INTEL_MSIC_VAUDACNT 0x0db +#define INTEL_MSIC_VHSPCNT 0x0dc +#define INTEL_MSIC_VHSNCNT 0x0dd +#define INTEL_MSIC_VHDMICNT 0x0de +#define INTEL_MSIC_VOTGCNT 0x0df +#define INTEL_MSIC_V1P35CNT 0x0e0 +#define INTEL_MSIC_V330AONCNT 0x0e1 + +/* RESET */ +#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */ +#define INTEL_MSIC_ERCONFIG 0x101 + +/* BURST */ +#define INTEL_MSIC_BATCURRENTLIMIT12 0x102 +#define INTEL_MSIC_BATTIMELIMIT12 0x103 +#define INTEL_MSIC_BATTIMELIMIT3 0x104 +#define INTEL_MSIC_BATTIMEDB 0x105 +#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106 +#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107 +#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108 + +/* RTC */ +#define INTEL_MSIC_RTCB1 0x140 /* RO */ +#define INTEL_MSIC_RTCB2 0x141 /* RO */ +#define INTEL_MSIC_RTCB3 0x142 /* RO */ +#define INTEL_MSIC_RTCB4 0x143 /* RO */ +#define INTEL_MSIC_RTCOB1 0x144 +#define INTEL_MSIC_RTCOB2 0x145 +#define INTEL_MSIC_RTCOB3 0x146 +#define INTEL_MSIC_RTCOB4 0x147 +#define INTEL_MSIC_RTCAB1 0x148 +#define INTEL_MSIC_RTCAB2 0x149 +#define INTEL_MSIC_RTCAB3 0x14a +#define INTEL_MSIC_RTCAB4 0x14b +#define INTEL_MSIC_RTCWAB1 0x14c +#define INTEL_MSIC_RTCWAB2 0x14d +#define INTEL_MSIC_RTCWAB3 0x14e +#define INTEL_MSIC_RTCWAB4 0x14f +#define INTEL_MSIC_RTCSC1 0x150 +#define INTEL_MSIC_RTCSC2 0x151 +#define INTEL_MSIC_RTCSC3 0x152 +#define INTEL_MSIC_RTCSC4 0x153 +#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */ +#define INTEL_MSIC_RTCCONFIG1 0x155 +#define INTEL_MSIC_RTCCONFIG2 0x156 + +/* CHARGER */ +#define INTEL_MSIC_BDTIMER 0x180 +#define INTEL_MSIC_BATTRMV 0x181 +#define INTEL_MSIC_VBUSDET 0x182 +#define INTEL_MSIC_VBUSDET1 0x183 +#define INTEL_MSIC_ADPHVDET 0x184 +#define INTEL_MSIC_ADPLVDET 0x185 +#define INTEL_MSIC_ADPDETDBDM 0x186 +#define INTEL_MSIC_LOWBATTDET 0x187 +#define INTEL_MSIC_CHRCTRL 0x188 +#define INTEL_MSIC_CHRCVOLTAGE 0x189 +#define INTEL_MSIC_CHRCCURRENT 0x18a +#define INTEL_MSIC_SPCHARGER 0x18b +#define INTEL_MSIC_CHRTTIME 0x18c +#define INTEL_MSIC_CHRCTRL1 0x18d +#define INTEL_MSIC_PWRSRCLMT 0x18e +#define INTEL_MSIC_CHRSTWDT 0x18f +#define INTEL_MSIC_WDTWRITE 0x190 /* WO */ +#define INTEL_MSIC_CHRSAFELMT 0x191 +#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */ +#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */ +#define INTEL_MSIC_CHRLEDPWM 0x194 +#define INTEL_MSIC_CHRLEDCTRL 0x195 + +/* ADC */ +#define INTEL_MSIC_ADC1CNTL1 0x1c0 +#define INTEL_MSIC_ADC1CNTL2 0x1c1 +#define INTEL_MSIC_ADC1CNTL3 0x1c2 +#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */ +#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */ +#define INTEL_MSIC_ADC1ADDR0 0x1c5 +#define INTEL_MSIC_ADC1ADDR1 0x1c6 +#define INTEL_MSIC_ADC1ADDR2 0x1c7 +#define INTEL_MSIC_ADC1ADDR3 0x1c8 +#define INTEL_MSIC_ADC1ADDR4 0x1c9 +#define INTEL_MSIC_ADC1ADDR5 0x1ca +#define INTEL_MSIC_ADC1ADDR6 0x1cb +#define INTEL_MSIC_ADC1ADDR7 0x1cc +#define INTEL_MSIC_ADC1ADDR8 0x1cd +#define INTEL_MSIC_ADC1ADDR9 0x1ce +#define INTEL_MSIC_ADC1ADDR10 0x1cf +#define INTEL_MSIC_ADC1ADDR11 0x1d0 +#define INTEL_MSIC_ADC1ADDR12 0x1d1 +#define INTEL_MSIC_ADC1ADDR13 0x1d2 +#define INTEL_MSIC_ADC1ADDR14 0x1d3 +#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */ +#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */ +#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */ +#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */ +#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */ +#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */ +#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */ +#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */ +#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */ +#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */ +#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */ +#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */ +#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */ +#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */ +#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */ +#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */ +#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */ +#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */ +#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */ +#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */ +#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */ +#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */ +#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */ +#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */ +#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */ +#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */ +#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */ +#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */ +#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */ +#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */ +#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */ +#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */ +#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */ +#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */ +#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */ +#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */ +#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */ +#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */ +#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */ +#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */ +#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */ +#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */ +#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */ +#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */ +#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */ +#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */ +#define INTEL_MSIC_CCCNTL 0x202 +#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */ +#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */ +#define INTEL_MSIC_CCADCHA 0x205 /* RO */ +#define INTEL_MSIC_CCADCLA 0x206 /* RO */ + +/* AUDIO */ +#define INTEL_MSIC_AUDPLLCTRL 0x240 +#define INTEL_MSIC_DMICBUF0123 0x241 +#define INTEL_MSIC_DMICBUF45 0x242 +#define INTEL_MSIC_DMICGPO 0x244 +#define INTEL_MSIC_DMICMUX 0x245 +#define INTEL_MSIC_DMICCLK 0x246 +#define INTEL_MSIC_MICBIAS 0x247 +#define INTEL_MSIC_ADCCONFIG 0x248 +#define INTEL_MSIC_MICAMP1 0x249 +#define INTEL_MSIC_MICAMP2 0x24a +#define INTEL_MSIC_NOISEMUX 0x24b +#define INTEL_MSIC_AUDIOMUX12 0x24c +#define INTEL_MSIC_AUDIOMUX34 0x24d +#define INTEL_MSIC_AUDIOSINC 0x24e +#define INTEL_MSIC_AUDIOTXEN 0x24f +#define INTEL_MSIC_HSEPRXCTRL 0x250 +#define INTEL_MSIC_IHFRXCTRL 0x251 +#define INTEL_MSIC_VOICETXVOL 0x252 +#define INTEL_MSIC_SIDETONEVOL 0x253 +#define INTEL_MSIC_MUSICSHARVOL 0x254 +#define INTEL_MSIC_VOICETXCTRL 0x255 +#define INTEL_MSIC_HSMIXER 0x256 +#define INTEL_MSIC_DACCONFIG 0x257 +#define INTEL_MSIC_SOFTMUTE 0x258 +#define INTEL_MSIC_HSLVOLCTRL 0x259 +#define INTEL_MSIC_HSRVOLCTRL 0x25a +#define INTEL_MSIC_IHFLVOLCTRL 0x25b +#define INTEL_MSIC_IHFRVOLCTRL 0x25c +#define INTEL_MSIC_DRIVEREN 0x25d +#define INTEL_MSIC_LINEOUTCTRL 0x25e +#define INTEL_MSIC_VIB1CTRL1 0x25f +#define INTEL_MSIC_VIB1CTRL2 0x260 +#define INTEL_MSIC_VIB1CTRL3 0x261 +#define INTEL_MSIC_VIB1SPIPCM_1 0x262 +#define INTEL_MSIC_VIB1SPIPCM_2 0x263 +#define INTEL_MSIC_VIB1CTRL5 0x264 +#define INTEL_MSIC_VIB2CTRL1 0x265 +#define INTEL_MSIC_VIB2CTRL2 0x266 +#define INTEL_MSIC_VIB2CTRL3 0x267 +#define INTEL_MSIC_VIB2SPIPCM_1 0x268 +#define INTEL_MSIC_VIB2SPIPCM_2 0x269 +#define INTEL_MSIC_VIB2CTRL5 0x26a +#define INTEL_MSIC_BTNCTRL1 0x26b +#define INTEL_MSIC_BTNCTRL2 0x26c +#define INTEL_MSIC_PCM1TXSLOT01 0x26d +#define INTEL_MSIC_PCM1TXSLOT23 0x26e +#define INTEL_MSIC_PCM1TXSLOT45 0x26f +#define INTEL_MSIC_PCM1RXSLOT0123 0x270 +#define INTEL_MSIC_PCM1RXSLOT045 0x271 +#define INTEL_MSIC_PCM2TXSLOT01 0x272 +#define INTEL_MSIC_PCM2TXSLOT23 0x273 +#define INTEL_MSIC_PCM2TXSLOT45 0x274 +#define INTEL_MSIC_PCM2RXSLOT01 0x275 +#define INTEL_MSIC_PCM2RXSLOT23 0x276 +#define INTEL_MSIC_PCM2RXSLOT45 0x277 +#define INTEL_MSIC_PCM1CTRL1 0x278 +#define INTEL_MSIC_PCM1CTRL2 0x279 +#define INTEL_MSIC_PCM1CTRL3 0x27a +#define INTEL_MSIC_PCM2CTRL1 0x27b +#define INTEL_MSIC_PCM2CTRL2 0x27c + +/* HDMI */ +#define INTEL_MSIC_HDMIPUEN 0x280 +#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */ + +/* Physical address of the start of the MSIC interrupt tree in SRAM */ +#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0 + +/** + * struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver + * @gpio_base: base number for the GPIOs + */ +struct intel_msic_gpio_pdata { + unsigned gpio_base; +}; + +/** + * struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver + * @gpio: GPIO number used for OCD interrupts + * + * The MSIC MFD driver converts @gpio into an IRQ number and passes it to + * the OCD driver as %IORESOURCE_IRQ. + */ +struct intel_msic_ocd_pdata { + unsigned gpio; +}; + +/* MSIC embedded blocks (subdevices) */ +enum intel_msic_block { + INTEL_MSIC_BLOCK_TOUCH, + INTEL_MSIC_BLOCK_ADC, + INTEL_MSIC_BLOCK_BATTERY, + INTEL_MSIC_BLOCK_GPIO, + INTEL_MSIC_BLOCK_AUDIO, + INTEL_MSIC_BLOCK_HDMI, + INTEL_MSIC_BLOCK_THERMAL, + INTEL_MSIC_BLOCK_POWER_BTN, + INTEL_MSIC_BLOCK_OCD, + + INTEL_MSIC_BLOCK_LAST, +}; + +/** + * struct intel_msic_platform_data - platform data for the MSIC driver + * @irq: array of interrupt numbers, one per device. If @irq is set to %0 + * for a given block, the corresponding platform device is not + * created. For devices which don't have an interrupt, use %0xff + * (this is same as in SFI spec). + * @gpio: platform data for the MSIC GPIO driver + * @ocd: platform data for the MSIC OCD driver + * + * Once the MSIC driver is initialized, the register interface is ready to + * use. All the platform devices for subdevices are created after the + * register interface is ready so that we can guarantee its availability to + * the subdevice drivers. + * + * Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ + * resources of the created platform device. + */ +struct intel_msic_platform_data { + int irq[INTEL_MSIC_BLOCK_LAST]; + struct intel_msic_gpio_pdata *gpio; + struct intel_msic_ocd_pdata *ocd; +}; + +struct intel_msic; + +extern int intel_msic_reg_read(unsigned short reg, u8 *val); +extern int intel_msic_reg_write(unsigned short reg, u8 val); +extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask); +extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count); +extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count); + +/* + * pdev_to_intel_msic - gets an MSIC instance from the platform device + * @pdev: platform device pointer + * + * The client drivers need to have pointer to the MSIC instance if they + * want to call intel_msic_irq_read(). This macro can be used for + * convenience to get the MSIC pointer from @pdev where needed. This is + * _only_ valid for devices which are managed by the MSIC. + */ +#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent)) + +extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, + u8 *val); + +#endif /* __LINUX_MFD_INTEL_MSIC_H__ */ -- cgit v1.2.1 From 3d5e2cabf11a65685e5067382ba4c4a76f18fcb7 Mon Sep 17 00:00:00 2001 From: Mattias Wallin Date: Thu, 22 Sep 2011 08:22:18 +0200 Subject: mfd: ab5500 chip register access The analog baseband chip ab5500 is a multi functional chip containing regulators, charging, gpio, USB and accessory detect. It also contain various multimedia functionalities like digital encoder and audio codec. The core driver added with this patch provides register access via i2c via PRCMU. Event handling implemented as irq_chip will come in future patches since it depends on PRCMU functionality not yet implemented. Signed-off-by: Mattias Wallin Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/ab5500/ab5500.h | 140 ++++++++++++++++++++++++++++++++++++++ include/linux/mfd/abx500.h | 4 +- 2 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 include/linux/mfd/ab5500/ab5500.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/ab5500/ab5500.h b/include/linux/mfd/ab5500/ab5500.h new file mode 100644 index 000000000000..a720051ae933 --- /dev/null +++ b/include/linux/mfd/ab5500/ab5500.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) ST-Ericsson 2011 + * + * License Terms: GNU General Public License v2 + */ +#ifndef MFD_AB5500_H +#define MFD_AB5500_H + +#include + +enum ab5500_devid { + AB5500_DEVID_ADC, + AB5500_DEVID_LEDS, + AB5500_DEVID_POWER, + AB5500_DEVID_REGULATORS, + AB5500_DEVID_SIM, + AB5500_DEVID_RTC, + AB5500_DEVID_CHARGER, + AB5500_DEVID_FUELGAUGE, + AB5500_DEVID_VIBRATOR, + AB5500_DEVID_CODEC, + AB5500_DEVID_USB, + AB5500_DEVID_OTP, + AB5500_DEVID_VIDEO, + AB5500_DEVID_DBIECI, + AB5500_DEVID_ONSWA, + AB5500_NUM_DEVICES, +}; + +enum ab5500_banks { + AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0, + AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1, + AB5500_BANK_VDENC = 2, + AB5500_BANK_SIM_USBSIM = 3, + AB5500_BANK_LED = 4, + AB5500_BANK_ADC = 5, + AB5500_BANK_RTC = 6, + AB5500_BANK_STARTUP = 7, + AB5500_BANK_DBI_ECI = 8, + AB5500_BANK_CHG = 9, + AB5500_BANK_FG_BATTCOM_ACC = 10, + AB5500_BANK_USB = 11, + AB5500_BANK_IT = 12, + AB5500_BANK_VIBRA = 13, + AB5500_BANK_AUDIO_HEADSETUSB = 14, + AB5500_NUM_BANKS = 15, +}; + +enum ab5500_banks_addr { + AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A, + AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B, + AB5500_ADDR_VDENC = 0x06, + AB5500_ADDR_SIM_USBSIM = 0x04, + AB5500_ADDR_LED = 0x10, + AB5500_ADDR_ADC = 0x0A, + AB5500_ADDR_RTC = 0x0F, + AB5500_ADDR_STARTUP = 0x03, + AB5500_ADDR_DBI_ECI = 0x07, + AB5500_ADDR_CHG = 0x0B, + AB5500_ADDR_FG_BATTCOM_ACC = 0x0C, + AB5500_ADDR_USB = 0x05, + AB5500_ADDR_IT = 0x0E, + AB5500_ADDR_VIBRA = 0x02, + AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D, +}; + +/* + * Interrupt register offsets + * Bank : 0x0E + */ +#define AB5500_IT_SOURCE0_REG 0x20 +#define AB5500_IT_SOURCE1_REG 0x21 +#define AB5500_IT_SOURCE2_REG 0x22 +#define AB5500_IT_SOURCE3_REG 0x23 +#define AB5500_IT_SOURCE4_REG 0x24 +#define AB5500_IT_SOURCE5_REG 0x25 +#define AB5500_IT_SOURCE6_REG 0x26 +#define AB5500_IT_SOURCE7_REG 0x27 +#define AB5500_IT_SOURCE8_REG 0x28 +#define AB5500_IT_SOURCE9_REG 0x29 +#define AB5500_IT_SOURCE10_REG 0x2A +#define AB5500_IT_SOURCE11_REG 0x2B +#define AB5500_IT_SOURCE12_REG 0x2C +#define AB5500_IT_SOURCE13_REG 0x2D +#define AB5500_IT_SOURCE14_REG 0x2E +#define AB5500_IT_SOURCE15_REG 0x2F +#define AB5500_IT_SOURCE16_REG 0x30 +#define AB5500_IT_SOURCE17_REG 0x31 +#define AB5500_IT_SOURCE18_REG 0x32 +#define AB5500_IT_SOURCE19_REG 0x33 +#define AB5500_IT_SOURCE20_REG 0x34 +#define AB5500_IT_SOURCE21_REG 0x35 +#define AB5500_IT_SOURCE22_REG 0x36 +#define AB5500_IT_SOURCE23_REG 0x37 + +#define AB5500_NUM_IRQ_REGS 23 + +/** + * struct ab5500 + * @access_mutex: lock out concurrent accesses to the AB registers + * @dev: a pointer to the device struct for this chip driver + * @ab5500_irq: the analog baseband irq + * @irq_base: the platform configuration irq base for subdevices + * @chip_name: name of this chip variant + * @chip_id: 8 bit chip ID for this chip variant + * @irq_lock: a lock to protect the mask + * @abb_events: a local bit mask of the prcmu wakeup events + * @event_mask: a local copy of the mask event registers + * @last_event_mask: a copy of the last event_mask written to hardware + * @startup_events: a copy of the first reading of the event registers + * @startup_events_read: whether the first events have been read + */ +struct ab5500 { + struct mutex access_mutex; + struct device *dev; + unsigned int ab5500_irq; + unsigned int irq_base; + char chip_name[32]; + u8 chip_id; + struct mutex irq_lock; + u32 abb_events; + u8 mask[AB5500_NUM_IRQ_REGS]; + u8 oldmask[AB5500_NUM_IRQ_REGS]; + u8 startup_events[AB5500_NUM_IRQ_REGS]; + bool startup_events_read; +#ifdef CONFIG_DEBUG_FS + unsigned int debug_bank; + unsigned int debug_address; +#endif +}; + +struct ab5500_platform_data { + struct {unsigned int base; unsigned int count; } irq; + void *dev_data[AB5500_NUM_DEVICES]; + struct abx500_init_settings *init_settings; + unsigned int init_settings_sz; + bool pm_power_off; +}; + +#endif /* MFD_AB5500_H */ diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 896b5e47f16e..79ec2c7b5fab 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -31,8 +31,8 @@ #define AB3100_R2B 0xc8 #define AB3550_P1A 0x10 #define AB5500_1_0 0x20 -#define AB5500_2_0 0x21 -#define AB5500_2_1 0x22 +#define AB5500_1_1 0x21 +#define AB5500_2_0 0x24 /* AB8500 CIDs*/ #define AB8500_CUTEARLY 0x00 -- cgit v1.2.1 From 8959e74399c798b45c0f5d477972b927c28f8dc9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 26 Sep 2011 11:45:30 +0200 Subject: mfd: Delete ab3550 driver The AB3550 never passed the prototype stage. Instead it was used as a precursor to AB5500 for testing basic building blocks used in that chip, since they had large similarities. Since AB3550 will not see the light of day in product form and since the prototypes are no longer used, let's delete the driver and any references to it. Cc: Mattias Wallin Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/abx500.h | 48 +--------------------------------------------- 1 file changed, 1 insertion(+), 47 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 79ec2c7b5fab..6d096e8b7746 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -6,7 +6,7 @@ * * ABX500 core access functions. * The abx500 interface is used for the Analog Baseband chip - * ab3100, ab3550, ab5500, and ab8500. + * ab3100, ab5500, and ab8500. * * Author: Mattias Wallin * Author: Mattias Nilsson @@ -29,7 +29,6 @@ #define AB3100_P1G 0xc6 #define AB3100_R2A 0xc7 #define AB3100_R2B 0xc8 -#define AB3550_P1A 0x10 #define AB5500_1_0 0x20 #define AB5500_1_1 0x21 #define AB5500_2_0 0x24 @@ -143,39 +142,6 @@ int ab3100_event_register(struct ab3100 *ab3100, int ab3100_event_unregister(struct ab3100 *ab3100, struct notifier_block *nb); -/* AB3550, STR register flags */ -#define AB3550_STR_ONSWA (0x01) -#define AB3550_STR_ONSWB (0x02) -#define AB3550_STR_ONSWC (0x04) -#define AB3550_STR_DCIO (0x08) -#define AB3550_STR_BOOT_MODE (0x10) -#define AB3550_STR_SIM_OFF (0x20) -#define AB3550_STR_BATT_REMOVAL (0x40) -#define AB3550_STR_VBUS (0x80) - -/* Interrupt mask registers */ -#define AB3550_IMR1 0x29 -#define AB3550_IMR2 0x2a -#define AB3550_IMR3 0x2b -#define AB3550_IMR4 0x2c -#define AB3550_IMR5 0x2d - -enum ab3550_devid { - AB3550_DEVID_ADC, - AB3550_DEVID_DAC, - AB3550_DEVID_LEDS, - AB3550_DEVID_POWER, - AB3550_DEVID_REGULATORS, - AB3550_DEVID_SIM, - AB3550_DEVID_UART, - AB3550_DEVID_RTC, - AB3550_DEVID_CHARGER, - AB3550_DEVID_FUELGAUGE, - AB3550_DEVID_VIBRATOR, - AB3550_DEVID_CODEC, - AB3550_NUM_DEVICES, -}; - /** * struct abx500_init_setting * Initial value of the registers for driver to use during setup. @@ -186,18 +152,6 @@ struct abx500_init_settings { u8 setting; }; -/** - * struct ab3550_platform_data - * Data supplied to initialize board connections to the AB3550 - */ -struct ab3550_platform_data { - struct {unsigned int base; unsigned int count; } irq; - void *dev_data[AB3550_NUM_DEVICES]; - size_t dev_data_sz[AB3550_NUM_DEVICES]; - struct abx500_init_settings *init_settings; - unsigned int init_settings_sz; -}; - int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, u8 value); int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, -- cgit v1.2.1 From fea799e3d3ab84ac675de7e48a13a79fb76b6e63 Mon Sep 17 00:00:00 2001 From: Mattias Nilsson Date: Fri, 12 Aug 2011 10:28:02 +0200 Subject: mfd: Create a common interface for dbx500 PRCMU drivers This adds a header file that contains the set of functions and definitions that will be shared between the DB8500 and DB5500 PRCMU drivers. Signed-off-by: Mattias Nilsson Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/dbx500-prcmu.h | 549 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 549 insertions(+) create mode 100644 include/linux/mfd/dbx500-prcmu.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h new file mode 100644 index 000000000000..6c7584d69d8f --- /dev/null +++ b/include/linux/mfd/dbx500-prcmu.h @@ -0,0 +1,549 @@ +/* + * Copyright (C) ST Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * + * STE Ux500 PRCMU API + */ +#ifndef __MACH_PRCMU_H +#define __MACH_PRCMU_H + +#include +#include +#include + +/* PRCMU Wakeup defines */ +enum prcmu_wakeup_index { + PRCMU_WAKEUP_INDEX_RTC, + PRCMU_WAKEUP_INDEX_RTT0, + PRCMU_WAKEUP_INDEX_RTT1, + PRCMU_WAKEUP_INDEX_HSI0, + PRCMU_WAKEUP_INDEX_HSI1, + PRCMU_WAKEUP_INDEX_USB, + PRCMU_WAKEUP_INDEX_ABB, + PRCMU_WAKEUP_INDEX_ABB_FIFO, + PRCMU_WAKEUP_INDEX_ARM, + PRCMU_WAKEUP_INDEX_CD_IRQ, + NUM_PRCMU_WAKEUP_INDICES +}; +#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) + +/* EPOD (power domain) IDs */ + +/* + * DB8500 EPODs + * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP + * - EPOD_ID_SVAPIPE: power domain for SVA pipe + * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP + * - EPOD_ID_SIAPIPE: power domain for SIA pipe + * - EPOD_ID_SGA: power domain for SGA + * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE + * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 + * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 + * - NUM_EPOD_ID: number of power domains + * + * TODO: These should be prefixed. + */ +#define EPOD_ID_SVAMMDSP 0 +#define EPOD_ID_SVAPIPE 1 +#define EPOD_ID_SIAMMDSP 2 +#define EPOD_ID_SIAPIPE 3 +#define EPOD_ID_SGA 4 +#define EPOD_ID_B2R2_MCDE 5 +#define EPOD_ID_ESRAM12 6 +#define EPOD_ID_ESRAM34 7 +#define NUM_EPOD_ID 8 + +/* + * DB5500 EPODs + */ +#define DB5500_EPOD_ID_BASE 0x0100 +#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0) +#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1) +#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2) +#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3) +#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6) +#define DB5500_NUM_EPOD_ID 7 + +/* + * state definition for EPOD (power domain) + * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged + * - EPOD_STATE_OFF: The EPOD is switched off + * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in + * retention + * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off + * - EPOD_STATE_ON: Same as above, but with clock enabled + */ +#define EPOD_STATE_NO_CHANGE 0x00 +#define EPOD_STATE_OFF 0x01 +#define EPOD_STATE_RAMRET 0x02 +#define EPOD_STATE_ON_CLK_OFF 0x03 +#define EPOD_STATE_ON 0x04 + +/* + * CLKOUT sources + */ +#define PRCMU_CLKSRC_CLK38M 0x00 +#define PRCMU_CLKSRC_ACLK 0x01 +#define PRCMU_CLKSRC_SYSCLK 0x02 +#define PRCMU_CLKSRC_LCDCLK 0x03 +#define PRCMU_CLKSRC_SDMMCCLK 0x04 +#define PRCMU_CLKSRC_TVCLK 0x05 +#define PRCMU_CLKSRC_TIMCLK 0x06 +#define PRCMU_CLKSRC_CLK009 0x07 +/* These are only valid for CLKOUT1: */ +#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 +#define PRCMU_CLKSRC_I2CCLK 0x41 +#define PRCMU_CLKSRC_MSP02CLK 0x42 +#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 +#define PRCMU_CLKSRC_HSIRXCLK 0x44 +#define PRCMU_CLKSRC_HSITXCLK 0x45 +#define PRCMU_CLKSRC_ARMCLKFIX 0x46 +#define PRCMU_CLKSRC_HDMICLK 0x47 + +/* + * Clock identifiers. + */ +enum prcmu_clock { + PRCMU_SGACLK, + PRCMU_UARTCLK, + PRCMU_MSP02CLK, + PRCMU_MSP1CLK, + PRCMU_I2CCLK, + PRCMU_SDMMCCLK, + PRCMU_SLIMCLK, + PRCMU_PER1CLK, + PRCMU_PER2CLK, + PRCMU_PER3CLK, + PRCMU_PER5CLK, + PRCMU_PER6CLK, + PRCMU_PER7CLK, + PRCMU_LCDCLK, + PRCMU_BMLCLK, + PRCMU_HSITXCLK, + PRCMU_HSIRXCLK, + PRCMU_HDMICLK, + PRCMU_APEATCLK, + PRCMU_APETRACECLK, + PRCMU_MCDECLK, + PRCMU_IPI2CCLK, + PRCMU_DSIALTCLK, + PRCMU_DMACLK, + PRCMU_B2R2CLK, + PRCMU_TVCLK, + PRCMU_SSPCLK, + PRCMU_RNGCLK, + PRCMU_UICCCLK, + PRCMU_PWMCLK, + PRCMU_IRDACLK, + PRCMU_IRRCCLK, + PRCMU_SIACLK, + PRCMU_SVACLK, + PRCMU_NUM_REG_CLOCKS, + PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, + PRCMU_TIMCLK, + PRCMU_PLLSOC0, + PRCMU_PLLSOC1, + PRCMU_PLLDDR, +}; + +/** + * enum ape_opp - APE OPP states definition + * @APE_OPP_INIT: + * @APE_NO_CHANGE: The APE operating point is unchanged + * @APE_100_OPP: The new APE operating point is ape100opp + * @APE_50_OPP: 50% + */ +enum ape_opp { + APE_OPP_INIT = 0x00, + APE_NO_CHANGE = 0x01, + APE_100_OPP = 0x02, + APE_50_OPP = 0x03 +}; + +/** + * enum arm_opp - ARM OPP states definition + * @ARM_OPP_INIT: + * @ARM_NO_CHANGE: The ARM operating point is unchanged + * @ARM_100_OPP: The new ARM operating point is arm100opp + * @ARM_50_OPP: The new ARM operating point is arm50opp + * @ARM_MAX_OPP: Operating point is "max" (more than 100) + * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 + * @ARM_EXTCLK: The new ARM operating point is armExtClk + */ +enum arm_opp { + ARM_OPP_INIT = 0x00, + ARM_NO_CHANGE = 0x01, + ARM_100_OPP = 0x02, + ARM_50_OPP = 0x03, + ARM_MAX_OPP = 0x04, + ARM_MAX_FREQ100OPP = 0x05, + ARM_EXTCLK = 0x07 +}; + +/** + * enum ddr_opp - DDR OPP states definition + * @DDR_100_OPP: The new DDR operating point is ddr100opp + * @DDR_50_OPP: The new DDR operating point is ddr50opp + * @DDR_25_OPP: The new DDR operating point is ddr25opp + */ +enum ddr_opp { + DDR_100_OPP = 0x00, + DDR_50_OPP = 0x01, + DDR_25_OPP = 0x02, +}; + +/* + * Definitions for controlling ESRAM0 in deep sleep. + */ +#define ESRAM0_DEEP_SLEEP_STATE_OFF 1 +#define ESRAM0_DEEP_SLEEP_STATE_RET 2 + +/** + * enum ddr_pwrst - DDR power states definition + * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged + * @DDR_PWR_STATE_ON: + * @DDR_PWR_STATE_OFFLOWLAT: + * @DDR_PWR_STATE_OFFHIGHLAT: + */ +enum ddr_pwrst { + DDR_PWR_STATE_UNCHANGED = 0x00, + DDR_PWR_STATE_ON = 0x01, + DDR_PWR_STATE_OFFLOWLAT = 0x02, + DDR_PWR_STATE_OFFHIGHLAT = 0x03 +}; + +#include +#include + +#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) + +static inline void __init prcmu_early_init(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_early_init(); + else + return db8500_prcmu_early_init(); +} + +static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + if (machine_is_u5500()) + return db5500_prcmu_set_power_state(state, keep_ulp_clk, + keep_ap_pll); + else + return db8500_prcmu_set_power_state(state, keep_ulp_clk, + keep_ap_pll); +} + +static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) +{ + if (machine_is_u5500()) + return db5500_prcmu_set_epod(epod_id, epod_state); + else + return db8500_prcmu_set_epod(epod_id, epod_state); +} + +static inline void prcmu_enable_wakeups(u32 wakeups) +{ + if (machine_is_u5500()) + db5500_prcmu_enable_wakeups(wakeups); + else + db8500_prcmu_enable_wakeups(wakeups); +} + +static inline void prcmu_disable_wakeups(void) +{ + prcmu_enable_wakeups(0); +} + +static inline void prcmu_config_abb_event_readout(u32 abb_events) +{ + if (machine_is_u5500()) + db5500_prcmu_config_abb_event_readout(abb_events); + else + db8500_prcmu_config_abb_event_readout(abb_events); +} + +static inline void prcmu_get_abb_event_buffer(void __iomem **buf) +{ + if (machine_is_u5500()) + db5500_prcmu_get_abb_event_buffer(buf); + else + db8500_prcmu_get_abb_event_buffer(buf); +} + +int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); +int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); + +int prcmu_config_clkout(u8 clkout, u8 source, u8 div); + +static inline int prcmu_request_clock(u8 clock, bool enable) +{ + if (machine_is_u5500()) + return db5500_prcmu_request_clock(clock, enable); + else + return db8500_prcmu_request_clock(clock, enable); +} + +int prcmu_set_ape_opp(u8 opp); +int prcmu_get_ape_opp(void); +int prcmu_set_ddr_opp(u8 opp); +int prcmu_get_ddr_opp(void); + +static inline int prcmu_set_arm_opp(u8 opp) +{ + if (machine_is_u5500()) + return db5500_prcmu_set_arm_opp(opp); + else + return db8500_prcmu_set_arm_opp(opp); +} + +static inline int prcmu_get_arm_opp(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_get_arm_opp(); + else + return db8500_prcmu_get_arm_opp(); +} + +static inline void prcmu_system_reset(u16 reset_code) +{ + if (machine_is_u5500()) + return db5500_prcmu_system_reset(reset_code); + else + return db8500_prcmu_system_reset(reset_code); +} + +static inline u16 prcmu_get_reset_code(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_get_reset_code(); + else + return db8500_prcmu_get_reset_code(); +} + +void prcmu_ac_wake_req(void); +void prcmu_ac_sleep_req(void); +void prcmu_modem_reset(void); +static inline bool prcmu_is_ac_wake_requested(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_is_ac_wake_requested(); + else + return db8500_prcmu_is_ac_wake_requested(); +} + +static inline int prcmu_set_display_clocks(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_set_display_clocks(); + else + return db8500_prcmu_set_display_clocks(); +} + +static inline int prcmu_disable_dsipll(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_disable_dsipll(); + else + return db8500_prcmu_disable_dsipll(); +} + +static inline int prcmu_enable_dsipll(void) +{ + if (machine_is_u5500()) + return db5500_prcmu_enable_dsipll(); + else + return db8500_prcmu_enable_dsipll(); +} + +static inline int prcmu_config_esram0_deep_sleep(u8 state) +{ + if (machine_is_u5500()) + return db5500_prcmu_config_esram0_deep_sleep(state); + else + return db8500_prcmu_config_esram0_deep_sleep(state); +} +#else + +static inline void __init prcmu_early_init(void) {} + +static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + return 0; +} + +static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) +{ + return 0; +} + +static inline void prcmu_enable_wakeups(u32 wakeups) {} + +static inline void prcmu_disable_wakeups(void) {} + +static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) +{ + return -ENOSYS; +} + +static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) +{ + return -ENOSYS; +} + +static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) +{ + return 0; +} + +static inline int prcmu_request_clock(u8 clock, bool enable) +{ + return 0; +} + +static inline int prcmu_set_ape_opp(u8 opp) +{ + return 0; +} + +static inline int prcmu_get_ape_opp(void) +{ + return APE_100_OPP; +} + +static inline int prcmu_set_arm_opp(u8 opp) +{ + return 0; +} + +static inline int prcmu_get_arm_opp(void) +{ + return ARM_100_OPP; +} + +static inline int prcmu_set_ddr_opp(u8 opp) +{ + return 0; +} + +static inline int prcmu_get_ddr_opp(void) +{ + return DDR_100_OPP; +} + +static inline void prcmu_system_reset(u16 reset_code) {} + +static inline u16 prcmu_get_reset_code(void) +{ + return 0; +} + +static inline void prcmu_ac_wake_req(void) {} + +static inline void prcmu_ac_sleep_req(void) {} + +static inline void prcmu_modem_reset(void) {} + +static inline bool prcmu_is_ac_wake_requested(void) +{ + return false; +} + +static inline int prcmu_set_display_clocks(void) +{ + return 0; +} + +static inline int prcmu_disable_dsipll(void) +{ + return 0; +} + +static inline int prcmu_enable_dsipll(void) +{ + return 0; +} + +static inline int prcmu_config_esram0_deep_sleep(u8 state) +{ + return 0; +} + +static inline void prcmu_config_abb_event_readout(u32 abb_events) {} + +static inline void prcmu_get_abb_event_buffer(void __iomem **buf) +{ + *buf = NULL; +} + +#endif + +/* PRCMU QoS APE OPP class */ +#define PRCMU_QOS_APE_OPP 1 +#define PRCMU_QOS_DDR_OPP 2 +#define PRCMU_QOS_DEFAULT_VALUE -1 + +#ifdef CONFIG_UX500_PRCMU_QOS_POWER + +unsigned long prcmu_qos_get_cpufreq_opp_delay(void); +void prcmu_qos_set_cpufreq_opp_delay(unsigned long); +void prcmu_qos_force_opp(int, s32); +int prcmu_qos_requirement(int pm_qos_class); +int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); +int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); +void prcmu_qos_remove_requirement(int pm_qos_class, char *name); +int prcmu_qos_add_notifier(int prcmu_qos_class, + struct notifier_block *notifier); +int prcmu_qos_remove_notifier(int prcmu_qos_class, + struct notifier_block *notifier); + +#else + +static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) +{ + return 0; +} + +static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} + +static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} + +static inline int prcmu_qos_requirement(int prcmu_qos_class) +{ + return 0; +} + +static inline int prcmu_qos_add_requirement(int prcmu_qos_class, + char *name, s32 value) +{ + return 0; +} + +static inline int prcmu_qos_update_requirement(int prcmu_qos_class, + char *name, s32 new_value) +{ + return 0; +} + +static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) +{ +} + +static inline int prcmu_qos_add_notifier(int prcmu_qos_class, + struct notifier_block *notifier) +{ + return 0; +} +static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, + struct notifier_block *notifier) +{ + return 0; +} + +#endif + +#endif /* __MACH_PRCMU_H */ -- cgit v1.2.1 From 73180f85f4ffbb66843f8248811b2ade29b22df2 Mon Sep 17 00:00:00 2001 From: Mattias Nilsson Date: Fri, 12 Aug 2011 10:28:10 +0200 Subject: mfd: Move to the new db500 PRCMU API Now that we have a shared API between the DB8500 and DB5500 PRCMU's, switch to using this neutral API instead. We delete the parts of db8500-prcmu.h that is now PRCMU-neutral, and calls will be diverted to respective driver. Common registers are in dbx500-prcmu-regs.h and common accessors and defines in This way we get a a lot more abstraction and code reuse. Signed-off-by: Mattias Nilsson Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/db5500-prcmu.h | 102 +++++++++-- include/linux/mfd/db8500-prcmu.h | 368 +++++++++------------------------------ include/linux/mfd/dbx500-prcmu.h | 8 +- 3 files changed, 174 insertions(+), 304 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h index f0977986402c..9890687f582d 100644 --- a/include/linux/mfd/db5500-prcmu.h +++ b/include/linux/mfd/db5500-prcmu.h @@ -5,21 +5,35 @@ * * U5500 PRCMU API. */ -#ifndef __MACH_PRCMU_U5500_H -#define __MACH_PRCMU_U5500_H +#ifndef __MFD_DB5500_PRCMU_H +#define __MFD_DB5500_PRCMU_H -#ifdef CONFIG_UX500_SOC_DB5500 +#ifdef CONFIG_MFD_DB5500_PRCMU void db5500_prcmu_early_init(void); - +int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state); +int db5500_prcmu_set_display_clocks(void); +int db5500_prcmu_disable_dsipll(void); +int db5500_prcmu_enable_dsipll(void); int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); +void db5500_prcmu_enable_wakeups(u32 wakeups); +int db5500_prcmu_request_clock(u8 clock, bool enable); +void db5500_prcmu_config_abb_event_readout(u32 abb_events); +void db5500_prcmu_get_abb_event_buffer(void __iomem **buf); +int prcmu_resetout(u8 resoutn, u8 state); +int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll); +int db5500_prcmu_config_esram0_deep_sleep(u8 state); +void db5500_prcmu_system_reset(u16 reset_code); +u16 db5500_prcmu_get_reset_code(void); +bool db5500_prcmu_is_ac_wake_requested(void); +int db5500_prcmu_set_arm_opp(u8 opp); +int db5500_prcmu_get_arm_opp(void); #else /* !CONFIG_UX500_SOC_DB5500 */ -static inline void db5500_prcmu_early_init(void) -{ -} +static inline void db5500_prcmu_early_init(void) {} static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) { @@ -31,15 +45,75 @@ static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) return -ENOSYS; } -#endif /* CONFIG_UX500_SOC_DB5500 */ +static inline int db5500_prcmu_request_clock(u8 clock, bool enable) +{ + return 0; +} + +static inline int db5500_prcmu_set_display_clocks(void) +{ + return 0; +} + +static inline int db5500_prcmu_disable_dsipll(void) +{ + return 0; +} + +static inline int db5500_prcmu_enable_dsipll(void) +{ + return 0; +} -static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events) +static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) { -#ifdef CONFIG_MACH_U5500_SIMULATOR return 0; -#else - return -1; -#endif } -#endif /* __MACH_PRCMU_U5500_H */ +static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} + +static inline int prcmu_resetout(u8 resoutn, u8 state) +{ + return 0; +} + +static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) +{ + return 0; +} + +static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {} +static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {} + +static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + return 0; +} + +static inline void db5500_prcmu_system_reset(u16 reset_code) {} + +static inline u16 db5500_prcmu_get_reset_code(void) +{ + return 0; +} + +static inline bool db5500_prcmu_is_ac_wake_requested(void) +{ + return 0; +} + +static inline int db5500_prcmu_set_arm_opp(u8 opp) +{ + return 0; +} + +static inline int db5500_prcmu_get_arm_opp(void) +{ + return 0; +} + + +#endif /* CONFIG_MFD_DB5500_PRCMU */ + +#endif /* __MFD_DB5500_PRCMU_H */ diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 917dbcab701c..60d27f7bfc1f 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -11,7 +11,6 @@ #define __MFD_DB8500_PRCMU_H #include -#include /* This portion previously known as */ @@ -133,7 +132,7 @@ enum ap_pwrst { * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle */ enum ap_pwrst_trans { - NO_TRANSITION = 0x00, + PRCMU_AP_NO_CHANGE = 0x00, APEXECUTE_TO_APSLEEP = 0x01, APIDLE_TO_APSLEEP = 0x02, /* To be removed */ PRCMU_AP_SLEEP = 0x01, @@ -145,54 +144,6 @@ enum ap_pwrst_trans { PRCMU_AP_DEEP_IDLE = 0x07, }; -/** - * enum ddr_pwrst - DDR power states definition - * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged - * @DDR_PWR_STATE_ON: - * @DDR_PWR_STATE_OFFLOWLAT: - * @DDR_PWR_STATE_OFFHIGHLAT: - */ -enum ddr_pwrst { - DDR_PWR_STATE_UNCHANGED = 0x00, - DDR_PWR_STATE_ON = 0x01, - DDR_PWR_STATE_OFFLOWLAT = 0x02, - DDR_PWR_STATE_OFFHIGHLAT = 0x03 -}; - -/** - * enum arm_opp - ARM OPP states definition - * @ARM_OPP_INIT: - * @ARM_NO_CHANGE: The ARM operating point is unchanged - * @ARM_100_OPP: The new ARM operating point is arm100opp - * @ARM_50_OPP: The new ARM operating point is arm50opp - * @ARM_MAX_OPP: Operating point is "max" (more than 100) - * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 - * @ARM_EXTCLK: The new ARM operating point is armExtClk - */ -enum arm_opp { - ARM_OPP_INIT = 0x00, - ARM_NO_CHANGE = 0x01, - ARM_100_OPP = 0x02, - ARM_50_OPP = 0x03, - ARM_MAX_OPP = 0x04, - ARM_MAX_FREQ100OPP = 0x05, - ARM_EXTCLK = 0x07 -}; - -/** - * enum ape_opp - APE OPP states definition - * @APE_OPP_INIT: - * @APE_NO_CHANGE: The APE operating point is unchanged - * @APE_100_OPP: The new APE operating point is ape100opp - * @APE_50_OPP: 50% - */ -enum ape_opp { - APE_OPP_INIT = 0x00, - APE_NO_CHANGE = 0x01, - APE_100_OPP = 0x02, - APE_50_OPP = 0x03 -}; - /** * enum hw_acc_state - State definition for hardware accelerator * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged @@ -469,26 +420,6 @@ enum auto_enable { /* End of file previously known as prcmu-fw-defs_v1.h */ -/* PRCMU Wakeup defines */ -enum prcmu_wakeup_index { - PRCMU_WAKEUP_INDEX_RTC, - PRCMU_WAKEUP_INDEX_RTT0, - PRCMU_WAKEUP_INDEX_RTT1, - PRCMU_WAKEUP_INDEX_HSI0, - PRCMU_WAKEUP_INDEX_HSI1, - PRCMU_WAKEUP_INDEX_USB, - PRCMU_WAKEUP_INDEX_ABB, - PRCMU_WAKEUP_INDEX_ABB_FIFO, - PRCMU_WAKEUP_INDEX_ARM, - NUM_PRCMU_WAKEUP_INDICES -}; -#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) - -/* PRCMU QoS APE OPP class */ -#define PRCMU_QOS_APE_OPP 1 -#define PRCMU_QOS_DDR_OPP 2 -#define PRCMU_QOS_DEFAULT_VALUE -1 - /** * enum hw_acc_dev - enum for hw accelerators * @HW_ACC_SVAMMDSP: for SVAMMDSP @@ -526,64 +457,6 @@ enum hw_acc_dev { NUM_HW_ACC }; -/* - * Ids for all EPODs (power domains) - * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP - * - EPOD_ID_SVAPIPE: power domain for SVA pipe - * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP - * - EPOD_ID_SIAPIPE: power domain for SIA pipe - * - EPOD_ID_SGA: power domain for SGA - * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE - * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 - * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 - * - NUM_EPOD_ID: number of power domains - */ -#define EPOD_ID_SVAMMDSP 0 -#define EPOD_ID_SVAPIPE 1 -#define EPOD_ID_SIAMMDSP 2 -#define EPOD_ID_SIAPIPE 3 -#define EPOD_ID_SGA 4 -#define EPOD_ID_B2R2_MCDE 5 -#define EPOD_ID_ESRAM12 6 -#define EPOD_ID_ESRAM34 7 -#define NUM_EPOD_ID 8 - -/* - * state definition for EPOD (power domain) - * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged - * - EPOD_STATE_OFF: The EPOD is switched off - * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in - * retention - * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off - * - EPOD_STATE_ON: Same as above, but with clock enabled - */ -#define EPOD_STATE_NO_CHANGE 0x00 -#define EPOD_STATE_OFF 0x01 -#define EPOD_STATE_RAMRET 0x02 -#define EPOD_STATE_ON_CLK_OFF 0x03 -#define EPOD_STATE_ON 0x04 - -/* - * CLKOUT sources - */ -#define PRCMU_CLKSRC_CLK38M 0x00 -#define PRCMU_CLKSRC_ACLK 0x01 -#define PRCMU_CLKSRC_SYSCLK 0x02 -#define PRCMU_CLKSRC_LCDCLK 0x03 -#define PRCMU_CLKSRC_SDMMCCLK 0x04 -#define PRCMU_CLKSRC_TVCLK 0x05 -#define PRCMU_CLKSRC_TIMCLK 0x06 -#define PRCMU_CLKSRC_CLK009 0x07 -/* These are only valid for CLKOUT1: */ -#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 -#define PRCMU_CLKSRC_I2CCLK 0x41 -#define PRCMU_CLKSRC_MSP02CLK 0x42 -#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 -#define PRCMU_CLKSRC_HSIRXCLK 0x44 -#define PRCMU_CLKSRC_HSITXCLK 0x45 -#define PRCMU_CLKSRC_ARMCLKFIX 0x46 -#define PRCMU_CLKSRC_HDMICLK 0x47 - /* * Definitions for autonomous power management configuration. */ @@ -620,88 +493,12 @@ struct prcmu_auto_pm_config { u8 sva_policy; }; -/** - * enum ddr_opp - DDR OPP states definition - * @DDR_100_OPP: The new DDR operating point is ddr100opp - * @DDR_50_OPP: The new DDR operating point is ddr50opp - * @DDR_25_OPP: The new DDR operating point is ddr25opp - */ -enum ddr_opp { - DDR_100_OPP = 0x00, - DDR_50_OPP = 0x01, - DDR_25_OPP = 0x02, -}; - -/* - * Clock identifiers. - */ -enum prcmu_clock { - PRCMU_SGACLK, - PRCMU_UARTCLK, - PRCMU_MSP02CLK, - PRCMU_MSP1CLK, - PRCMU_I2CCLK, - PRCMU_SDMMCCLK, - PRCMU_SLIMCLK, - PRCMU_PER1CLK, - PRCMU_PER2CLK, - PRCMU_PER3CLK, - PRCMU_PER5CLK, - PRCMU_PER6CLK, - PRCMU_PER7CLK, - PRCMU_LCDCLK, - PRCMU_BMLCLK, - PRCMU_HSITXCLK, - PRCMU_HSIRXCLK, - PRCMU_HDMICLK, - PRCMU_APEATCLK, - PRCMU_APETRACECLK, - PRCMU_MCDECLK, - PRCMU_IPI2CCLK, - PRCMU_DSIALTCLK, - PRCMU_DMACLK, - PRCMU_B2R2CLK, - PRCMU_TVCLK, - PRCMU_SSPCLK, - PRCMU_RNGCLK, - PRCMU_UICCCLK, - PRCMU_NUM_REG_CLOCKS, - PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, - PRCMU_TIMCLK, -}; - -/* - * Definitions for controlling ESRAM0 in deep sleep. - */ -#define ESRAM0_DEEP_SLEEP_STATE_OFF 1 -#define ESRAM0_DEEP_SLEEP_STATE_RET 2 - -#ifdef CONFIG_MFD_DB8500_PRCMU -void __init prcmu_early_init(void); -int prcmu_set_display_clocks(void); -int prcmu_disable_dsipll(void); -int prcmu_enable_dsipll(void); -#else -static inline void __init prcmu_early_init(void) {} -#endif - #ifdef CONFIG_MFD_DB8500_PRCMU +void db8500_prcmu_early_init(void); int prcmu_set_rc_a2p(enum romcode_write); enum romcode_read prcmu_get_rc_p2a(void); enum ap_pwrst prcmu_get_xp70_current_state(void); -int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); - -void prcmu_enable_wakeups(u32 wakeups); -static inline void prcmu_disable_wakeups(void) -{ - prcmu_enable_wakeups(0); -} - -void prcmu_config_abb_event_readout(u32 abb_events); -void prcmu_get_abb_event_buffer(void __iomem **buf); -int prcmu_set_arm_opp(u8 opp); -int prcmu_get_arm_opp(void); bool prcmu_has_arm_maxopp(void); bool prcmu_is_u8400(void); int prcmu_set_ape_opp(u8 opp); @@ -710,19 +507,14 @@ int prcmu_request_ape_opp_100_voltage(bool enable); int prcmu_release_usb_wakeup_state(void); int prcmu_set_ddr_opp(u8 opp); int prcmu_get_ddr_opp(void); -unsigned long prcmu_qos_get_cpufreq_opp_delay(void); -void prcmu_qos_set_cpufreq_opp_delay(unsigned long); /* NOTE! Use regulator framework instead */ int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); -int prcmu_set_epod(u16 epod_id, u8 epod_state); void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, struct prcmu_auto_pm_config *idle); bool prcmu_is_auto_pm_enabled(void); int prcmu_config_clkout(u8 clkout, u8 source, u8 div); -int prcmu_request_clock(u8 clock, bool enable); int prcmu_set_clock_divider(u8 clock, u8 divider); -int prcmu_config_esram0_deep_sleep(u8 state); int prcmu_config_hotdog(u8 threshold); int prcmu_config_hotmon(u8 low, u8 high); int prcmu_start_temp_sense(u16 cycles32k); @@ -732,14 +524,36 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); -void prcmu_system_reset(u16 reset_code); void prcmu_modem_reset(void); -bool prcmu_is_ac_wake_requested(void); void prcmu_enable_spi2(void); void prcmu_disable_spi2(void); +int prcmu_config_a9wdog(u8 num, bool sleep_auto_off); +int prcmu_enable_a9wdog(u8 id); +int prcmu_disable_a9wdog(u8 id); +int prcmu_kick_a9wdog(u8 id); +int prcmu_load_a9wdog(u8 id, u32 val); + +void db8500_prcmu_system_reset(u16 reset_code); +int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +void db8500_prcmu_enable_wakeups(u32 wakeups); +int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); +int db8500_prcmu_request_clock(u8 clock, bool enable); +int db8500_prcmu_set_display_clocks(void); +int db8500_prcmu_disable_dsipll(void); +int db8500_prcmu_enable_dsipll(void); +void db8500_prcmu_config_abb_event_readout(u32 abb_events); +void db8500_prcmu_get_abb_event_buffer(void __iomem **buf); +int db8500_prcmu_config_esram0_deep_sleep(u8 state); +u16 db8500_prcmu_get_reset_code(void); +bool db8500_prcmu_is_ac_wake_requested(void); +int db8500_prcmu_set_arm_opp(u8 opp); +int db8500_prcmu_get_arm_opp(void); + #else /* !CONFIG_MFD_DB8500_PRCMU */ +static inline void db8500_prcmu_early_init(void) {} + static inline int prcmu_set_rc_a2p(enum romcode_write code) { return 0; @@ -755,34 +569,12 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void) return AP_EXECUTE; } -static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, - bool keep_ap_pll) -{ - return 0; -} - -static inline void prcmu_enable_wakeups(u32 wakeups) {} - -static inline void prcmu_disable_wakeups(void) {} - -static inline void prcmu_config_abb_event_readout(u32 abb_events) {} - -static inline int prcmu_set_arm_opp(u8 opp) -{ - return 0; -} - -static inline int prcmu_get_arm_opp(void) -{ - return ARM_100_OPP; -} - -static bool prcmu_has_arm_maxopp(void) +static inline bool prcmu_has_arm_maxopp(void) { return false; } -static bool prcmu_is_u8400(void) +static inline bool prcmu_is_u8400(void) { return false; } @@ -817,13 +609,6 @@ static inline int prcmu_get_ddr_opp(void) return DDR_100_OPP; } -static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) -{ - return 0; -} - -static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} - static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state) { return 0; @@ -844,21 +629,11 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) return 0; } -static inline int prcmu_request_clock(u8 clock, bool enable) -{ - return 0; -} - static inline int prcmu_set_clock_divider(u8 clock, u8 divider) { return 0; } -int prcmu_config_esram0_deep_sleep(u8 state) -{ - return 0; -} - static inline int prcmu_config_hotdog(u8 threshold) { return 0; @@ -893,86 +668,107 @@ static inline void prcmu_ac_wake_req(void) {} static inline void prcmu_ac_sleep_req(void) {} -static inline void prcmu_system_reset(u16 reset_code) {} - static inline void prcmu_modem_reset(void) {} -static inline bool prcmu_is_ac_wake_requested(void) +static inline int prcmu_enable_spi2(void) { - return false; + return 0; } -#ifndef CONFIG_UX500_SOC_DB5500 -static inline int prcmu_set_display_clocks(void) +static inline int prcmu_disable_spi2(void) { return 0; } -static inline int prcmu_disable_dsipll(void) +static inline void db8500_prcmu_system_reset(u16 reset_code) {} + +static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) { return 0; } -static inline int prcmu_enable_dsipll(void) +static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {} + +static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) { return 0; } -#endif -static inline int prcmu_enable_spi2(void) +static inline int db8500_prcmu_request_clock(u8 clock, bool enable) { return 0; } -static inline int prcmu_disable_spi2(void) +static inline int db8500_prcmu_set_display_clocks(void) { return 0; } -#endif /* !CONFIG_MFD_DB8500_PRCMU */ +static inline int db8500_prcmu_disable_dsipll(void) +{ + return 0; +} + +static inline int db8500_prcmu_enable_dsipll(void) +{ + return 0; +} + +static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state) +{ + return 0; +} + +static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {} -#ifdef CONFIG_UX500_PRCMU_QOS_POWER -int prcmu_qos_requirement(int pm_qos_class); -int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); -int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); -void prcmu_qos_remove_requirement(int pm_qos_class, char *name); -int prcmu_qos_add_notifier(int prcmu_qos_class, - struct notifier_block *notifier); -int prcmu_qos_remove_notifier(int prcmu_qos_class, - struct notifier_block *notifier); -#else -static inline int prcmu_qos_requirement(int prcmu_qos_class) +static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {} + +static inline u16 db8500_prcmu_get_reset_code(void) { return 0; } -static inline int prcmu_qos_add_requirement(int prcmu_qos_class, - char *name, s32 value) +static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) { return 0; } -static inline int prcmu_qos_update_requirement(int prcmu_qos_class, - char *name, s32 new_value) +static inline int prcmu_enable_a9wdog(u8 id) { return 0; } -static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) +static inline int prcmu_disable_a9wdog(u8 id) { + return 0; } -static inline int prcmu_qos_add_notifier(int prcmu_qos_class, - struct notifier_block *notifier) +static inline int prcmu_kick_a9wdog(u8 id) { return 0; } -static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, - struct notifier_block *notifier) + +static inline int prcmu_load_a9wdog(u8 id, u32 val) { return 0; } -#endif +static inline bool db8500_prcmu_is_ac_wake_requested(void) +{ + return 0; +} + +static inline int db8500_prcmu_set_arm_opp(u8 opp) +{ + return 0; +} + +static inline int db8500_prcmu_get_arm_opp(void) +{ + return 0; +} + +#endif /* !CONFIG_MFD_DB8500_PRCMU */ #endif /* __MFD_DB8500_PRCMU_H */ diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 6c7584d69d8f..bac942f959c1 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -240,7 +240,7 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { if (machine_is_u5500()) - return db5500_prcmu_set_epod(epod_id, epod_state); + return -EINVAL; else return db8500_prcmu_set_epod(epod_id, epod_state); } @@ -295,7 +295,7 @@ int prcmu_get_ddr_opp(void); static inline int prcmu_set_arm_opp(u8 opp) { if (machine_is_u5500()) - return db5500_prcmu_set_arm_opp(opp); + return -EINVAL; else return db8500_prcmu_set_arm_opp(opp); } @@ -303,7 +303,7 @@ static inline int prcmu_set_arm_opp(u8 opp) static inline int prcmu_get_arm_opp(void) { if (machine_is_u5500()) - return db5500_prcmu_get_arm_opp(); + return -EINVAL; else return db8500_prcmu_get_arm_opp(); } @@ -362,7 +362,7 @@ static inline int prcmu_enable_dsipll(void) static inline int prcmu_config_esram0_deep_sleep(u8 state) { if (machine_is_u5500()) - return db5500_prcmu_config_esram0_deep_sleep(state); + return -EINVAL; else return db8500_prcmu_config_esram0_deep_sleep(state); } -- cgit v1.2.1 From b958f7a7cbdfbf59ba61de7ebb9c59b0ee3a7967 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 30 Oct 2011 23:50:36 +0100 Subject: mfd: Fix missing abx500 header file updates I missed to include a patch adding the new silicon revision define CUT3P3 and remove the retired CUT0 versions of AB8500. Also delete the reference to the retired AB3550 from the header. Reported-by: Randy Dunlap Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/abx500.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 6d096e8b7746..9970337ff041 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -34,11 +34,11 @@ #define AB5500_2_0 0x24 /* AB8500 CIDs*/ -#define AB8500_CUTEARLY 0x00 #define AB8500_CUT1P0 0x10 #define AB8500_CUT1P1 0x11 #define AB8500_CUT2P0 0x20 #define AB8500_CUT3P0 0x30 +#define AB8500_CUT3P3 0x33 /* * AB3100, EVENTA1, A2 and A3 event register flags -- cgit v1.2.1 From 19940b3d55c87d8089a8cb0fa8e5a9918a3846bd Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 19 Aug 2011 18:05:05 +0900 Subject: ASoC: Ensure we get an impedence reported for WM8958 jack detect Occasionally we may see an accessory reported before we have a stable impedance for the accessory. If this happens then reread the status in order to ensure that the handler can take the appropriate action for the status change. Signed-off-by: Mark Brown --- include/linux/mfd/wm8994/registers.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index fae295048a8b..83a9caec0e43 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -1962,6 +1962,21 @@ #define WM8958_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ #define WM8958_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ +/* + * R210 (0xD2) - Mic Detect 3 + */ +#define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ +#define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ +#define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ +#define WM8958_MICD_VALID 0x0002 /* MICD_VALID */ +#define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */ +#define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */ +#define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */ +#define WM8958_MICD_STS 0x0001 /* MICD_STS */ +#define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */ +#define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */ +#define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */ + /* * R76 (0x4C) - Charge Pump (1) */ -- cgit v1.2.1