/*
 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc-msm8916.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/arm/qcom-ids.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM8916";
	compatible = "qcom,msm8916";
	qcom,msm-id =	<QCOM_ID_MSM8916 0>,
			<QCOM_ID_MSM8216 0>,
			<QCOM_ID_MSM8116 0>,
			<QCOM_ID_MSM8616 0>,
			<QCOM_ID_APQ8016 0>;


	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases { };

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		reserve_aligned@86000000 {
			reg = <0x0 0x86000000 0x0 0x0300000>;
			no-map;
		};

		smem_mem: smem_region@86300000 {
			reg = <0x0 0x86300000 0x0 0x0100000>;
			no-map;
		};

                hypervisor_mem: hypervisor_region@86400000 {
                        no-map;
                        reg = <0x0 0x86400000 0x0 0x0400000>;
                };

                peripheral_mem: peripheral_region@8b600000 {
                        no-map;
                        reg = <0x0 0x8b600000 0x0 0x0600000>;
                };

		vidc_mem: vidc_region@8f800000 {
			no-map;
			reg = <0 0x8f800000 0 0x800000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc0>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      power-domain = <&l2ccc_0>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x1>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc1>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x2>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc2>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x3>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc3>;
			next-level-cache = <&L2_0>;
			clocks = <&a53cc 1>;
			clock-latency = <200000>;
			cpu-supply = <&pm8916_s2>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};
	};

	cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 4>;

			trips {
				cpu_alert0: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 3>;

			trips {
				cpu_alert1: trip@0 {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip@1 {
					temperature = <125000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert1>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x1000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;

			blsp1_uart1_default: blsp1_uart1_default {
				pinmux {
					function = "blsp_uart1";
					//	TX, RX, CTS_N, RTS_N
					pins = "gpio0", "gpio1",
					       "gpio2", "gpio3";
				};
				pinconf {
					pins = "gpio0", "gpio1",
					       "gpio2", "gpio3";
					drive-strength = <16>;
					bias-disable;
				};
			};

			blsp1_uart1_sleep: blsp1_uart1_sleep {
				pinmux {
					function = "blsp_uart1";
					pins = "gpio0", "gpio1",
					       "gpio2", "gpio3";
				};
				pinconf {
					pins = "gpio0", "gpio1",
					       "gpio2", "gpio3";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			blsp1_uart2_default: blsp1_uart2_default {
				pinmux {
					function = "blsp_uart2";
					pins = "gpio4", "gpio5";
				};
				pinconf {
					pins = "gpio4", "gpio5";
					drive-strength = <16>;
					bias-disable;
				};
			};

			blsp1_uart2_sleep: blsp1_uart2_sleep {
				pinmux {
					function = "blsp_uart2";
					pins = "gpio4", "gpio5";
				};
				pinconf {
					pins = "gpio4", "gpio5";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			wcnss_default: wcnss_default {
				pinmux2 {
					function = "wcss_wlan";
					pins = "gpio40";
				};
				pinmux1 {
					function = "wcss_wlan";
					pins = "gpio41";
				};
				pinmux0 {
					function = "wcss_wlan";
					pins = "gpio42";
				};
				pinmux {
					function = "wcss_wlan";
					pins = "gpio43", "gpio44";
				};
				pinconf {
					pins = "gpio40", "gpio41", "gpio42", "gpio43",
					       "gpio44";
					drive-strength = <6>;
					bias-pull-up;
				};
			};

			spi1_default: spi1_default {
				pinmux {
					function = "blsp_spi1";
					pins = "gpio0", "gpio1", "gpio3";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio2";
				};
				pinconf {
					pins = "gpio0", "gpio1", "gpio3";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio2";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};

			spi1_sleep: spi1_sleep {
				pinmux {
					function = "gpio";
					pins = "gpio0", "gpio1", "gpio2", "gpio3";
				};
				pinconf {
					pins = "gpio0", "gpio1", "gpio2", "gpio3";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			spi2_default: spi2_default {
				pinmux {
					function = "blsp_spi2";
					pins = "gpio4", "gpio5", "gpio7";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio6";
				};
				pinconf {
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio6";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};

			spi2_sleep: spi2_sleep {
				pinmux {
					function = "gpio";
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
				};
				pinconf {
					pins = "gpio4", "gpio5", "gpio6", "gpio7";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			spi3_default: spi3_default {
				pinmux {
					function = "blsp_spi3";
					pins = "gpio8", "gpio9", "gpio11";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio10";
				};
				pinconf {
					pins = "gpio8", "gpio9", "gpio10", "gpio11";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio10";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};

			spi3_sleep: spi3_sleep {
				pinmux {
					function = "gpio";
					pins = "gpio8", "gpio9", "gpio10", "gpio11";
				};
				pinconf {
					pins = "gpio8", "gpio9", "gpio10", "gpio11";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			spi4_default: spi4_default {
				pinmux {
					function = "blsp_spi4";
					pins = "gpio12", "gpio13", "gpio15";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio14";
				};
				pinconf {
					pins = "gpio12", "gpio13", "gpio14", "gpio15";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio14";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};

			spi4_sleep: spi4_sleep {
				pinmux {
					function = "gpio";
					pins = "gpio12", "gpio13", "gpio14", "gpio15";
				};
				pinconf {
					pins = "gpio12", "gpio13", "gpio14", "gpio15";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			spi5_default: spi5_default {
				pinmux {
					function = "blsp_spi5";
					pins = "gpio16", "gpio17", "gpio19";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio18";
				};
				pinconf {
					pins = "gpio16", "gpio17", "gpio18", "gpio19";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio18";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};

			spi5_sleep: spi5_sleep {
				pinmux {
					function = "gpio";
					pins = "gpio16", "gpio17", "gpio18", "gpio19";
				};
				pinconf {
					pins = "gpio16", "gpio17", "gpio18", "gpio19";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			spi6_default: spi6_default {
				pinmux {
					function = "blsp_spi6";
					pins = "gpio20", "gpio21", "gpio23";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio22";
				};
				pinconf {
					pins = "gpio20", "gpio21", "gpio22", "gpio23";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio22";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};

			spi6_sleep: spi6_sleep {
				pinmux {
					function = "gpio";
					pins = "gpio20", "gpio21", "gpio22", "gpio23";
				};
				pinconf {
					pins = "gpio20", "gpio21", "gpio22", "gpio23";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			i2c0_default: i2c0_default {
				pinmux {
					function = "blsp_i2c2";
					pins = "gpio6", "gpio7";
				};
				pinconf {
					pins = "gpio6", "gpio7";
					drive-strength = <16>;
					bias-disable = <0>;
				};
			};

			i2c4_default: i2c4_default {
				pinmux {
					function = "blsp_i2c4";
					pins = "gpio14", "gpio15";
				};
				pinconf {
					pins = "gpio14", "gpio15";
					drive-strength = <16>;
					bias-disable = <0>;
				};
			};

			i2c4_sleep: i2c4_sleep {
				pinmux {
					function = "blsp_i2c4";
					pins = "gpio14", "gpio15";
				};
				pinconf {
					pins = "gpio14", "gpio15";
					drive-strength = <2>;
					bias-disable = <0>;
				};
			};

			i2c6_default: i2c6_default {
				pinmux {
					function = "blsp_i2c6";
					pins = "gpio22", "gpio23";
				};
				pinconf {
					pins = "gpio22", "gpio23";
					drive-strength = <16>;
					bias-disable = <0>;
				};
			};

	sdhc2_cd_pin {
		sdc2_cd_on: cd_on {
			pinmux {
				function = "gpio";
				pins = "gpio38";
			};
			pinconf {
				pins = "gpio38";
				drive-strength = <2>;
				bias-pull-up;
			};
		};
		sdc2_cd_off: cd_off {
			pinmux {
				function = "gpio";
				pins = "gpio38";
			};
			pinconf {
				pins = "gpio38";
				drive-strength = <2>;
				bias-disable;
			};
		};

	};

	pmx_sdc1_clk {
		sdc1_clk_on: clk_on {
			pinmux {
				pins = "sdc1_clk";
			};
			pinconf {
				pins = "sdc1_clk";
				bias-disable;
				drive-strength = <16>;
			};
		};
		sdc1_clk_off: clk_off {
			pinmux {
				pins = "sdc1_clk";
			};
			pinconf {
				pins = "sdc1_clk";
				bias-disable;
				drive-strength = <2>;
			};
		};
	};

	pmx_sdc1_cmd {
		sdc1_cmd_on: cmd_on {
			pinmux {
				pins = "sdc1_cmd";
			};
			pinconf {
				pins = "sdc1_cmd";
				bias-pull-up;
				drive-strength = <10>;
			};
		};
		sdc1_cmd_off: cmd_off {
			pinmux {
				pins = "sdc1_cmd";
			};
			pinconf {
				pins = "sdc1_cmd";
				bias-pull-up;
				drive-strength = <2>;
			};
		};
	};

	pmx_sdc1_data {
		sdc1_data_on: data_on {
			pinmux {
				pins = "sdc1_data";
			};
			pinconf {
				pins = "sdc1_data";
				bias-pull-up;
				drive-strength = <10>;
			};
		};
		sdc1_data_off: data_off {
			pinmux {
				pins = "sdc1_data";
			};
			pinconf {
				pins = "sdc1_data";
				bias-pull-up;
				drive-strength = <2>;
			};
		};
	};

	pmx_sdc2_clk {
		sdc2_clk_on: clk_on {
			pinmux {
				pins = "sdc2_clk";
			};
			pinconf {
				pins = "sdc2_clk";
				bias-disable;
				drive-strength = <16>;
			};
		};
		sdc2_clk_off: clk_off {
			pinmux {
				pins = "sdc2_clk";
			};
			pinconf {
				pins = "sdc2_clk";
				bias-disable;
				drive-strength = <2>;
			};
		};
	};

	pmx_sdc2_cmd {
		sdc2_cmd_on: cmd_on {
			pinmux {
				pins = "sdc2_cmd";
			};
			pinconf {
				pins = "sdc2_cmd";
				bias-pull-up;
				drive-strength = <10>;
			};
		};
		sdc2_cmd_off: cmd_off {
			pinmux {
				pins = "sdc2_cmd";
			};
			pinconf {
				pins = "sdc2_cmd";
				bias-pull-up;
				drive-strength = <2>;
			};
		};
	};

	pmx_sdc2_data {
		sdc2_data_on: data_on {
			pinmux {
				pins = "sdc2_data";
			};
			pinconf {
				pins = "sdc2_data";
				bias-pull-up;
				drive-strength = <10>;
			};
		};
		sdc2_data_off: data_off {
			pinmux {
				pins = "sdc2_data";
			};
			pinconf {
				pins = "sdc2_data";
				bias-pull-up;
				drive-strength = <2>;
			};
		};
	};

		ext-codec-lines {
			ext_codec_lines_act: lines_on {
				pinmux {
					function = "gpio";
					pins = "gpio67";
				};
				pinconf {
					pins = "gpio67";
					drive-strength = <8>;
					bias-disable;
					output-high;
				};
			};
			ext_codec_lines_sus: lines_off {
				pinmux {
					function = "gpio";
					pins = "gpio67";
				};
				pinconf {
					pins = "gpio67";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		cdc-pdm-lines {
			cdc_pdm_lines_act: pdm_lines_on {
				pinmux {
					function = "cdc_pdm0";
					pins = "gpio63", "gpio64", "gpio65", "gpio66",
					       "gpio67", "gpio68";
				};
				pinconf {
					pins = "gpio63", "gpio64", "gpio65", "gpio66",
					       "gpio67", "gpio68";
					drive-strength = <8>;
					bias-pull-none;
				};
			};
			cdc_pdm_lines_sus: pdm_lines_off {
				pinmux {
					function = "cdc_pdm0";
					pins = "gpio63", "gpio64", "gpio65", "gpio66",
					       "gpio67", "gpio68";
				};
				pinconf {
					pins = "gpio63", "gpio64", "gpio65", "gpio66",
					       "gpio67", "gpio68";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		ext-pri-tlmm-lines {
			ext_pri_tlmm_lines_act: ext_pa_on {
				pinmux {
					function = "pri_mi2s";
					pins = "gpio113", "gpio114", "gpio115",
					       "gpio116";
				};
				pinconf {
					pins = "gpio113", "gpio114", "gpio115",
					       "gpio116";
					drive-strength = <8>;
					bias-pull-none;
				};
			};

			ext_pri_tlmm_lines_sus: ext_pa_off {
				pinmux {
					function = "pri_mi2s";
					pins = "gpio113", "gpio114", "gpio115",
					       "gpio116";
				};
				pinconf {
					pins = "gpio113", "gpio114", "gpio115",
					       "gpio116";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		ext-pri-ws-line {
			ext_pri_ws_act: ext_pa_on {
				pinmux {
					function = "pri_mi2s_ws";
					pins = "gpio110";
				};
				pinconf {
					pins = "gpio110";
					drive-strength = <8>;
					bias-pull-none;
				};
			};

			ext_pri_ws_sus: ext_pa_off {
				pinmux {
					function = "pri_mi2s_ws";
					pins = "gpio110";
				};
				pinconf {
					pins = "gpio110";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		ext-mclk-tlmm-lines {
			ext_mclk_tlmm_lines_act: mclk_lines_on {
				pinmux {
					function = "pri_mi2s";
					pins = "gpio116";
				};
				pinconf {
					pins = "gpio116";
					drive-strength = <8>;
					bias-pull-none;
				};
			};
			ext_mclk_tlmm_lines_sus: mclk_lines_off {
				pinmux {
					function = "pri_mi2s";
					pins = "gpio116";
				};
				pinconf {
					pins = "gpio116";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		/* secondary Mi2S */
		ext-sec-tlmm-lines {
			ext_sec_tlmm_lines_act: tlmm_lines_on {
				pinmux {
					function = "sec_mi2s";
					pins = "gpio112", "gpio117", "gpio118",
					       "gpio119";
				};
				pinconf {
					pins = "gpio112", "gpio117", "gpio118",
						"gpio119";
					drive-strength = <8>;
					bias-pull-none;
				};
			};
			ext_sec_tlmm_lines_sus: tlmm_lines_off {
				pinmux {
					function = "sec_mi2s";
					pins = "gpio112", "gpio117", "gpio118",
					       "gpio119";
				};
				pinconf {
					pins = "gpio112", "gpio117", "gpio118",
						"gpio119";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		cdc-dmic-lines {
			cdc_dmic_lines_act: dmic_lines_on {
				pinmux_dmic0_clk {
					function = "dmic0_clk";
					pins = "gpio0";
				};
				pinmux_dmic0_data {
					function = "dmic0_data";
					pins = "gpio1";
				};
				pinconf {
					pins = "gpio0", "gpio1";
					drive-strength = <8>;
				};
			};
			cdc_dmic_lines_sus: dmic_lines_off {
				pinconf {
					pins = "gpio0", "gpio1";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		cross-conn-det {
			cross_conn_det_act: lines_on {
				pinmux {
					function = "gpio";
					pins = "gpio120";
				};
				pinconf {
					pins = "gpio120";
					drive-strength = <8>;
					output-low;
					bias-pull-down;
				};
			};
			cross_conn_det_sus: lines_off {
				pinmux {
					function = "gpio";
					pins = "gpio120";
				};
				pinconf {
					pins = "gpio120";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};
	};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
			reg = <0x1905000 0x20000>;
		};

		tcsr_mutex: hwlock {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_regs 0 0x1000>;
			#hwlock-cells = <1>;
		};

		smem {
			compatible = "qcom,smem";
			reg = <0x60000 0x8000>;
			reg-names = "aux-mem1";

			memory-region = <&smem_mem>;

			hwlocks = <&tcsr_mutex 3>;
		};


		apcs: syscon@b011000 {
			compatible = "syscon";
			reg = <0x0b011000 0x1000>;
		};

		smd {
			compatible = "qcom,smd";

			rpm {
				interrupts = <0 168 1>;
				qcom,ipc = <&apcs 8 0>;
				qcom,smd-edge = <15>;
				qcom,remote-pid = <0xffffffff>;

				rpm_requests {
					compatible = "qcom,rpm-msm8916";
					qcom,smd-channels = "rpm_requests";

					rpmcc: qcom,rpmcc {
						compatible = "qcom,rpmcc-msm8916";
						#clock-cells = <1>;
					};

					msm-bus {
						compatible = "qcom,rpm-msm-bus";
					};

					pm8916-regulators {
						compatible = "qcom,rpm-pm8916-regulators";

						vdd_l1_l2_l3-supply = <&pm8916_s3>;
						vdd_l5-supply = <&pm8916_s3>;
						vdd_l4_l5_l6-supply = <&pm8916_s4>;
						vdd_l7-supply = <&pm8916_s4>;

						pm8916_s1: s1 {
							regulator-min-microvolt = <375000>;
							regulator-max-microvolt = <1562000>;
						};
						s2 {
							regulator-min-microvolt = <375000>;
							regulator-max-microvolt = <1562000>;
						};
						pm8916_s3: s3 {
							regulator-min-microvolt = <375000>;
							regulator-max-microvolt = <1562000>;
						};
						pm8916_s4: s4 {
							regulator-min-microvolt = <1800000>;
							regulator-max-microvolt = <1800000>;
							regulator-always-on;
							regulator-boot-on;
						};

						pm8916_l1: l1 {
							regulator-min-microvolt = <375000>;
							regulator-max-microvolt = <1525000>;
						};
						pm8916_l2: l2 {
							regulator-min-microvolt = <375000>;
							regulator-max-microvolt = <1525000>;
						};
						pm8916_l3: l3 {
							regulator-min-microvolt = <375000>;
							regulator-max-microvolt = <1525000>;
						};
						pm8916_l4: l4 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l5: l5 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l6: l6 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l7: l7 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l8: l8 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l9: l9 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l10: l10 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l11: l11 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l12: l12 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l13: l13 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l14: l14 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l15: l15 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l16: l16 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l17: l17 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
						pm8916_l18: l18 {
							regulator-min-microvolt = <1750000>;
							regulator-max-microvolt = <3337000>;
						};
					};
				};
			};

			pronto_smd_edge: pronto {
				interrupts = <0 142 1>;

				qcom,ipc = <&apcs 8 17>;
				qcom,smd-edge = <6>;
				qcom,remote-pid = <4>;

				bt_cmd {
					compatible = "qcom,hci-smd-bt-cmd";
					qcom,smd-channels = "APPS_RIVA_BT_CMD";
				};

				bt_acl {
					compatible = "qcom,hci-smd-bt-acl";
					qcom,smd-channels = "APPS_RIVA_BT_ACL";
				};

				ipcrtr {
					compatible = "qcom,ipcrtr";
					qcom,smd-channels = "IPCRTR";
				};

				wifi {
					compatible = "qcom,wlan-ctrl";
					qcom,smd-channels = "WLAN_CTRL";

					interrupts = <0 145 0>, <0 146 0>;
					interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";

					qcom,wcnss_mmio = <0xfb000000 0x21b000>;

					// qcom,tx-enable-gpios = <&apps_smsm 10 0>;
					// qcom,tx-rings-empty-gpios = <&apps_smsm 9 0>;
				};

				wcnss_ctrl {
					compatible = "qcom,wcnss-ctrl";
					qcom,smd-channels = "WCNSS_CTRL";

					qcom,wcnss_mmio = <0xfb21b000 0x3000>;
				};
			};
		};

		gcc: qcom,gcc@1800000 {
			compatible = "qcom,gcc-msm8916";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x1800000 0x80000>;
		};

		a53cc: qcom,a53cc@0b016000 {
			compatible = "qcom,clock-a53-msm8916";
			reg = <0x0b016000 0x40>;
			#clock-cells = <1>;
			qcom,apcs = <&apcs>;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_default>;
			pinctrl-1 = <&spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi2: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_default>;
			pinctrl-1 = <&spi2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi3: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_default>;
			pinctrl-1 = <&spi3_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi4: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi4_default>;
			pinctrl-1 = <&spi4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi5: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi5_default>;
			pinctrl-1 = <&spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi6: spi@78ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078ba000 0x600>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi6_default>;
			pinctrl-1 = <&spi6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* BLSP1 QUP2 */
		blsp_i2c0: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b6000 0x1000>;
			interrupts = <GIC_SPI 96 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c4: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x1000>;
			interrupts = <GIC_SPI 98 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c6: i2c@78ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78ba000 0x1000>;
			interrupts = <GIC_SPI 100 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
		};

		l2ccc_0: clock-controller@b011000 {
			compatible = "qcom,8916-l2ccc";
			reg = <0x0b011000 0x1000>;
		};

		timer@b020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xb020000 0x1000>;
			clock-frequency = <19200000>;

			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb021000 0x1000>,
				      <0xb022000 0x1000>;
			};

			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb023000 0x1000>;
				status = "disabled";
			};

			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb024000 0x1000>;
				status = "disabled";
			};

			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb025000 0x1000>;
				status = "disabled";
			};

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb026000 0x1000>;
				status = "disabled";
			};

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb027000 0x1000>;
				status = "disabled";
			};

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb028000 0x1000>;
				status = "disabled";
			};
		};

		sdhc_1: sdhci@07824000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			bus-width = <8>;
			non-removable;
			status = "disabled";
		};

		sdhc_2: sdhci@07864000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			bus-width = <4>;
			status = "disabled";
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x200f000 0x001000>,
			      <0x2400000 0x400000>,
			      <0x2c00000 0x400000>,
			      <0x3800000 0x200000>,
			      <0x200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		usb_dev: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x78d9000 0x400>;
			dr_mode = "peripheral";
			interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
			usb-phy = <&usb_otg>;
			status = "disabled";
		};

		usb_host: ehci@78d9000 {
			compatible = "qcom,ehci-host";
			reg = <0x78d9000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
			usb-phy = <&usb_otg>;
			status = "disabled";
		};

		usb_otg: phy@78d9000 {
			compatible = "qcom,usb-otg-snps";
			reg = <0x78d9000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;

//			vddcx-supply = <&pm8916_s1_corner>;
			v1p8-supply = <&pm8916_l7>;
			v3p3-supply = <&pm8916_l13>;
			qcom,vdd-levels = <1 5 7>;

			qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
			dr_mode = "peripheral";
			qcom,otg-control = <2>; // PMIC
			qcom,manual-pullup;

			qcom,msm-bus,name = "usb2";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
					<87 512 0 0>,
					<87 512 80000 0>,
					<87 512 6000  6000>;

			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>,
				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
			clock-names = "iface", "core", "sleep";

			resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
			reset-names = "phy", "link";
			status = "disabled";
		};

		acc0: clock-controller@b088000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b088000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		acc1: clock-controller@b098000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b098000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		acc2: clock-controller@b0a8000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b0a8000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		acc3: clock-controller@b0b8000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b0b8000 0x1000>,
			      <0x0b008000 0x1000>;
		};

		/* Audio */

		lpass: lpass-cpu@07700000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

			clock-names = "ahbix-clk",
					"pcnoc-mport-clk",
					"pcnoc-sway-clk",
					"mi2s-bit-clk0",
					"mi2s-bit-clk1",
					"mi2s-bit-clk2",
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;

			interrupts = <0 160 0>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
			reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
		};

		sound: sound {
			status = "disabled";
			compatible = "qcom,apq8016-sbc-sndcard";
			reg = <0x07702000 0x4>, <0x07702004 0x4>;
			reg-names = "mic-iomux", "spkr-iomux";
		};

	        tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-msm8916", "syscon";
			reg = <0x1937000 0x30000>;
		};

		uqfprom: eeprom@58000 {
			compatible = "qcom,qfprom-msm8916";
			reg = <0x58000 0x7000>;
		};

		cpr@b018000 {
			compatible = "qcom,cpr";
			reg = <0xb018000 0x1000>;
			interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
			vdd-mx-supply = <&pm8916_l3>;
			acc-syscon = <&tcsr>;
			eeprom = <&uqfprom>;

			qcom,cpr-ref-clk = <19200>;
			qcom,cpr-timer-delay-us = <5000>;
			qcom,cpr-timer-cons-up = <0>;
			qcom,cpr-timer-cons-down = <2>;
			qcom,cpr-up-threshold = <0>;
			qcom,cpr-down-threshold = <2>;
			qcom,cpr-idle-clocks = <15>;
			qcom,cpr-gcnt-us = <1>;
			qcom,vdd-apc-step-up-limit = <1>;
			qcom,vdd-apc-step-down-limit = <1>;
			qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
		};

		qfprom: qfprom@5c000 {
			compatible = "qcom,qfprom";
			reg = <0x5c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_caldata: caldata@d0 {
				reg = <0xd0 0x8>;
			};
			tsens_calsel: calsel@ec {
				reg = <0xec 0x4>;
			};
		};

		tsens: thermal-sensor@4a8000 {
			compatible = "qcom,msm8916-tsens";
			reg = <0x4a8000 0x2000>;
			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
			nvmem-cell-names = "calib", "calib_sel";
			qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
			qcom,sensor-id = <0 1 2 4 5>;
			#thermal-sensor-cells = <1>;
		};

		wcnss-smp2p {
			compatible = "qcom,smp2p";
			qcom,smem = <451>, <431>;

			interrupts = <0 143 1>;

			qcom,ipc = <&apcs 8 18>;

			qcom,local-pid = <0>;
			qcom,remote-pid = <4>;

			wcnss_smp2p_out: master-kernel {
				qcom,entry-name = "master-kernel";
				qcom,outbound;

				gpio-controller;
				#gpio-cells = <2>;
			};

			wcnss_smp2p_in: slave-kernel {
				qcom,entry-name = "slave-kernel";
				qcom,inbound;

				interrupt-controller;
				#interrupt-cells = <2>;
			};
		};

		pronto_rproc: pronto_rproc {
			compatible = "qcom,tz-pil";

			interrupts-extended = <&intc 0 149 1>,
					      <&wcnss_smp2p_in 0 0>,
					      <&wcnss_smp2p_in 1 0>,
					      <&wcnss_smp2p_in 2 0>,
					      <&wcnss_smp2p_in 3 0>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc CRYPTO_CLK_SRC>;
			clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_src_clk";

			qcom,firmware-name = "wcnss";
			qcom,pas-id = <6>;

			qcom,crash-reason = <422>;
			qcom,smd-edges = <&pronto_smd_edge>;

			qcom,pll-supply = <&pm8916_l7>;
			qcom,pll-uV = <1800000>;
			qcom,pll-uA = <18000>;

			qcom,stop-gpio = <&wcnss_smp2p_out 0 0>;

			pinctrl-names = "default";
			pinctrl-0 = <&wcnss_default>;

			memory-region = <&peripheral_mem>;
		};

		vidc_rproc: vidc_tzpil@0 {
			compatible = "qcom,tz-pil";
			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc CRYPTO_CLK_SRC>;
			clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_src_clk";
			qcom,firmware-name = "venus";
			qcom,pas-id = <9>;
			memory-region = <&vidc_mem>;
			status = "disabled";
		};

		vidc: qcom,vidc@1d00000 {
			compatible = "qcom,msm-vidc";
			reg = <0x01d00000 0xff000>;
			interrupts = <GIC_SPI 44 0>;
			power-domains = <&gcc VENUS_GDSC>;
			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
				 <&gcc GCC_VENUS0_AHB_CLK>,
				 <&gcc GCC_VENUS0_AXI_CLK>;
			clock-names = "core_clk", "iface_clk", "bus_clk";
			qcom,hfi = "venus";
			qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
			qcom,enable-idle-indicator;
			rproc = <&vidc_rproc>;
			qcom,iommu-cb = <&venus_ns>, <&venus_sec_bitstream>,
					<&venus_sec_pixel>, <&venus_sec_non_pixel>;
			status = "disabled";
		};

                qcom,wcn36xx@0a000000 {
                        compatible = "qcom,wcn3620";
                        reg = <0x0a000000 0x280000>,
                                <0xb011008 0x04>,
                                <0x0a21b000 0x3000>,
                                <0x03204000 0x00000100>,
                                <0x03200800 0x00000200>,
                                <0x0A100400 0x00000200>,
                                <0x0A205050 0x00000200>,
                                <0x0A219000 0x00000020>,
                                <0x0A080488 0x00000008>,
                                <0x0A080fb0 0x00000008>,
                                <0x0A08040c 0x00000008>,
                                <0x0A0120a8 0x00000008>,
                                <0x0A012448 0x00000008>,
                                <0x0A080c00 0x00000001>;

                        reg-names = "wcnss_mmio", "wcnss_fiq",
                                    "pronto_phy_base", "riva_phy_base",
                                    "riva_ccu_base", "pronto_a2xb_base",
                                    "pronto_ccpu_base", "pronto_saw2_base",
                                    "wlan_tx_phy_aborts","wlan_brdg_err_source",
                                    "wlan_tx_status", "alarms_txctl",
                                    "alarms_tactl", "pronto_mcu_base";

                        interrupts = <0 145 0 0 146 0>;
                        interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";

                        // qcom,pronto-vddmx-supply = <&pm8916_l3>;
                        // qcom,pronto-vddcx-supply = <&pm8916_s1_corner>;
                        // qcom,pronto-vddpx-supply = <&pm8916_l7>;
                        // qcom,iris-vddxo-supply   = <&pm8916_l7>;
                        // qcom,iris-vddrfa-supply  = <&pm8916_s3>;
                        // qcom,iris-vddpa-supply   = <&pm8916_l9>;
                        // qcom,iris-vdddig-supply  = <&pm8916_l5>;

                        pinctrl-names = "wcnss_default";
                        // pinctrl-names = "wcnss_default", "wcnss_sleep",
                        //                                "wcnss_gpio_default";
                        pinctrl-0 = <&wcnss_default>;
                        // pinctrl-1 = <&wcnss_sleep>;
                        // pinctrl-2 = <&wcnss_gpio_default>;

                        // clocks = <&rpmcc RPM_XO_CLK_SRC>,
                        //         <&rpmcc RPM_RF_CLK2>;
                        //clock-names = "xo", "rf_clk";

			rproc = <&pronto_rproc>;
                        qcom,has-autodetect-xo;
                        qcom,wlan-rx-buff-count = <512>;
                        qcom,is-pronto-vt;
                        qcom,has-pronto-hw;
                        // qcom,wcnss-adc_tm = <&pm8916_adc_tm>;
                };



		qcom,rpm-log@29dc00 {
			compatible = "qcom,rpm-log";
			reg = <0x29dc00 0x4000>;
			qcom,rpm-addr-phys = <0x200000>;
			qcom,offset-version = <4>;
			qcom,offset-page-buffer-addr = <36>;
			qcom,offset-log-len = <40>;
			qcom,offset-log-len-mask = <44>;
			qcom,offset-page-indices = <56>;
		};
	};
};
#include "msm8916-iommu.dtsi"
#include "msm8916-bus.dtsi"