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author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:27:26 +0300 |
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committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:28:09 +0300 |
commit | 887acf6842cb48e7c51728ed8d81fc5ab0425403 (patch) | |
tree | fd458e6b01e27f5e0791c74316e93f83ae88075c | |
parent | dd8c8d4b7cee7cb58b40e0456d656d68a31ef3b4 (diff) | |
download | llvm-887acf6842cb48e7c51728ed8d81fc5ab0425403.tar.gz |
[X86][Costmodel] Load/store i16 Stride=6 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/YTeT9M7fW - for intels `Block RThroughput: <=212.0`; for ryzens, `Block RThroughput: <=64.0`
So could pick cost of `212`
For store we have:
https://godbolt.org/z/vc954KEGP - for intels `Block RThroughput: <=90.0`; for ryzens, `Block RThroughput: <=24.0`
So we could pick cost of `90`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111940
3 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 14b98f3c6590..6b0432f555d2 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5285,6 +5285,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 + {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 @@ -5389,6 +5390,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) + {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll index 7a9a052e8786..64dd8b185ecc 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll @@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 11 for VF 4 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 42 for VF 8 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 112 for VF 16 For instruction: %v0 = load i16, i16* %in0, align 2 -; AVX2: LV: Found an estimated cost of 516 for VF 32 For instruction: %v0 = load i16, i16* %in0, align 2 +; AVX2: LV: Found an estimated cost of 224 for VF 32 For instruction: %v0 = load i16, i16* %in0, align 2 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX512: LV: Found an estimated cost of 13 for VF 2 For instruction: %v0 = load i16, i16* %in0, align 2 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll index b4693d1c3916..05ace8cf2233 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll @@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 17 for VF 4 For instruction: store i16 %v5, i16* %out5, align 2 ; AVX2: LV: Found an estimated cost of 24 for VF 8 For instruction: store i16 %v5, i16* %out5, align 2 ; AVX2: LV: Found an estimated cost of 64 for VF 16 For instruction: store i16 %v5, i16* %out5, align 2 -; AVX2: LV: Found an estimated cost of 516 for VF 32 For instruction: store i16 %v5, i16* %out5, align 2 +; AVX2: LV: Found an estimated cost of 102 for VF 32 For instruction: store i16 %v5, i16* %out5, align 2 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v5, i16* %out5, align 2 ; AVX512: LV: Found an estimated cost of 13 for VF 2 For instruction: store i16 %v5, i16* %out5, align 2 |