diff options
author | Zarko Todorovski <zarko@ca.ibm.com> | 2021-11-17 21:59:00 -0500 |
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committer | Zarko Todorovski <zarko@ca.ibm.com> | 2021-11-17 21:59:00 -0500 |
commit | 5b8bbbecfae3bc1cb98726bd0b1ea829adb726be (patch) | |
tree | d076a8d72cf909854033cc7cc316833ae4a539b3 | |
parent | 4a9523c55fa11d85a4edbf24abc2c17bb3849fbc (diff) | |
download | llvm-5b8bbbecfae3bc1cb98726bd0b1ea829adb726be.tar.gz |
[NFC][llvm] Inclusive language: reword and remove uses of sanity in llvm/lib/Target
Reworded removed code comments that contain `sanity check` and `sanity
test`.
24 files changed, 31 insertions, 33 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 7c7867f508ca..6e9e61c8e7ac 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -8950,7 +8950,7 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, Src.WindowBase *= Src.WindowScale; } - // Final sanity check before we try to actually produce a shuffle. + // Final check before we try to actually produce a shuffle. LLVM_DEBUG(for (auto Src : Sources) assert(Src.ShuffleVec.getValueType() == ShuffleVT);); diff --git a/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp b/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp index 9125b37b50d4..80d98d17e1d6 100644 --- a/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp +++ b/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp @@ -641,7 +641,7 @@ bool AArch64SIMDInstrOpt::processSeqRegInst(MachineInstr *DefiningMI, StReg[i] = DefiningMI->getOperand(2*i+1).getReg(); StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); - // Sanity check for the other arguments. + // Validation check for the other arguments. if (DefiningMI->getOperand(2*i+2).isImm()) { switch (DefiningMI->getOperand(2*i+2).getImm()) { default: diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 7075247ff964..6d3aea2721de 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1511,7 +1511,7 @@ public: } bool isAdrpLabel() const { - // Validation was handled during parsing, so we just sanity check that + // Validation was handled during parsing, so we just verify that // something didn't go haywire. if (!isImm()) return false; @@ -1527,7 +1527,7 @@ public: } bool isAdrLabel() const { - // Validation was handled during parsing, so we just sanity check that + // Validation was handled during parsing, so we just verify that // something didn't go haywire. if (!isImm()) return false; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 580ba8815bce..da9bd112442a 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -2787,7 +2787,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { #ifndef NDEBUG const Register PtrReg = LdSt.getPointerReg(); const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); - // Sanity-check the pointer register. + // Check that the pointer register is valid. assert(PtrRB.getID() == AArch64::GPRRegBankID && "Load/Store pointer operand isn't a GPR"); assert(MRI.getType(PtrReg).isPointer() && diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp index ef86d760184a..3fad7e192195 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -225,7 +225,7 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) { EmitToStreamer(*OutStreamer, TmpInst); #ifdef EXPENSIVE_CHECKS - // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot + // Check getInstSizeInBytes on explicitly specified CPUs (it cannot // work correctly for the generic CPU). // // The isPseudo check really shouldn't be here, but unfortunately there are diff --git a/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp b/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp index 424c9fe60e43..ac6a3581e255 100644 --- a/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp +++ b/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp @@ -86,7 +86,7 @@ GetFunctionFromMDNode(MDNode *Node) { if (!F) return nullptr; - // Sanity checks. + // Validation checks. size_t ExpectNumArgNodeOps = F->arg_size() + 1; for (size_t i = 0; i < NumKernelArgMDNodes; ++i) { MDNode *ArgNode = dyn_cast_or_null<MDNode>(Node->getOperand(i + 1)); diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 6b1c5d56379f..a3a0e9c9b9ac 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -646,7 +646,7 @@ void SIFoldOperands::foldOperand( return; if (frameIndexMayFold(TII, *UseMI, UseOpIdx, OpToFold)) { - // Sanity check that this is a stack access. + // Verify that this is a stack access. // FIXME: Should probably use stack pseudos before frame lowering. if (TII->isMUBUF(*UseMI)) { diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp index 588fe5c84481..7fd08f70ea3b 100644 --- a/llvm/lib/Target/ARC/ARCISelLowering.cpp +++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp @@ -534,7 +534,7 @@ SDValue ARCTargetLowering::LowerCallArguments( CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1)); } } else { - // sanity check + // Only arguments passed on the stack should make it here. assert(VA.isMemLoc()); // Load the argument to a virtual register unsigned ObjSize = VA.getLocVT().getStoreSize(); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 493d7059490b..e7e10ce07a44 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4533,7 +4533,7 @@ SDValue ARMTargetLowering::LowerFormalArguments( InVals.push_back(ArgValue); } else { // VA.isRegLoc() - // sanity check + // Only arguments passed on the stack should make it here. assert(VA.isMemLoc()); assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); @@ -8105,7 +8105,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, Src.WindowBase *= Src.WindowScale; } - // Final sanity check before we try to actually produce a shuffle. + // Final check before we try to actually produce a shuffle. LLVM_DEBUG(for (auto Src : Sources) assert(Src.ShuffleVec.getValueType() == ShuffleVT);); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index b56e54ea13f2..851acea94022 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -331,7 +331,7 @@ void ARMAsmBackend::relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const { unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI); - // Sanity check w/ diagnostic if we get here w/ a bogus instruction. + // Return a diagnostic if we get here w/ a bogus instruction. if (RelaxedOp == Inst.getOpcode()) { SmallString<256> Tmp; raw_svector_ostream OS(Tmp); diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index cc328cdacbf6..a6f2afb87102 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -1200,7 +1200,7 @@ SDValue AVRTargetLowering::LowerFormalArguments( InVals.push_back(ArgValue); } else { - // Sanity check. + // Only arguments passed on the stack should make it here. assert(VA.isMemLoc()); EVT LocVT = VA.getLocVT(); diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 85c74b9a2425..90723ac04f64 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -822,7 +822,7 @@ BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB); } else { int64_t imm32 = MI.getOperand(2).getImm(); - // sanity check before we build J*_ri instruction. + // Check before we build J*_ri instruction. assert (isInt<32>(imm32)); BuildMI(BB, DL, TII.get(NewCC)) .addReg(LHS).addImm(imm32).addMBB(Copy1MBB); diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 145dd3528f68..0d9e63c112fb 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -486,7 +486,7 @@ SDValue LanaiTargetLowering::LowerCCCArguments( llvm_unreachable("unhandled argument type"); } } else { - // Sanity check + // Only arguments passed on the stack should make it here. assert(VA.isMemLoc()); // Load the argument to a virtual register unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 7dabb9b4abae..abd48dfd5139 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -304,13 +304,11 @@ static bool isValidIndexedLoad(const LoadSDNode *LD) { switch (VT.getSimpleVT().SimpleTy) { case MVT::i8: - // Sanity check if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1) return false; break; case MVT::i16: - // Sanity check if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2) return false; diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index 90645526799a..c64a44a0ef95 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -670,7 +670,7 @@ SDValue MSP430TargetLowering::LowerCCCArguments( InVals.push_back(ArgValue); } } else { - // Sanity check + // Only arguments passed on the stack should make it here. assert(VA.isMemLoc()); SDValue InVal; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index eda9f82ee4cd..4f364ef6afc7 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3717,7 +3717,7 @@ SDValue MipsTargetLowering::LowerFormalArguments( LocVT = VA.getValVT(); } - // sanity check + // Only arguments pased on the stack should make it here. assert(VA.isMemLoc()); // The stack pointer offset is relative to the caller stack frame. diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 04a835f08855..03a545605fe1 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -964,7 +964,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { // match the instruction. case MipsISD::Ins: { - // Sanity checking for the node operands. + // Validating the node operands. if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64) return false; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ec1dc39bbe77..2257e2f37173 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -7432,7 +7432,7 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant( else return false; - // Sanity check that our new mask is a subset of the demanded mask. + // Check that our new mask is a subset of the demanded mask. assert(IsLegalMask(NewMask)); return UseMask(NewMask); } diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index c8fe04389c48..ddcfb9da8249 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -99,7 +99,7 @@ static bool isUncondBranchOpcode(int Opc) { #define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t) // VE has other branch relative always instructions for word/double/float, - // but we use only long branches in our lower. So, sanity check it here. + // but we use only long branches in our lower. So, check it here. assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) && "Branch relative word/double/float always instructions should not be " "used!"); @@ -127,7 +127,7 @@ static bool isIndirectBranchOpcode(int Opc) { #define BRKIND(NAME) \ (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t) // VE has other branch always instructions for word/double/float, but - // we use only long branches in our lower. So, sanity check it here. + // we use only long branches in our lower. So, check it here. assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) && "Branch word/double/float always instructions should not be used!"); return BRKIND(BCFL); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp index c137f990ac58..7832f199a2cc 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp @@ -173,7 +173,7 @@ static bool explicitlyBranchesTo(MachineBasicBlock *Pred, // satisfying the restrictions given by BeforeSet and AfterSet. BeforeSet // contains instructions that should go before the marker, and AfterSet contains // ones that should go after the marker. In this function, AfterSet is only -// used for sanity checking. +// used for validation checking. template <typename Container> static MachineBasicBlock::iterator getEarliestInsertPos(MachineBasicBlock *MBB, const Container &BeforeSet, @@ -182,7 +182,7 @@ getEarliestInsertPos(MachineBasicBlock *MBB, const Container &BeforeSet, while (InsertPos != MBB->begin()) { if (BeforeSet.count(&*std::prev(InsertPos))) { #ifndef NDEBUG - // Sanity check + // Validation check for (auto Pos = InsertPos, E = MBB->begin(); Pos != E; --Pos) assert(!AfterSet.count(&*std::prev(Pos))); #endif @@ -197,7 +197,7 @@ getEarliestInsertPos(MachineBasicBlock *MBB, const Container &BeforeSet, // satisfying the restrictions given by BeforeSet and AfterSet. BeforeSet // contains instructions that should go before the marker, and AfterSet contains // ones that should go after the marker. In this function, BeforeSet is only -// used for sanity checking. +// used for validation checking. template <typename Container> static MachineBasicBlock::iterator getLatestInsertPos(MachineBasicBlock *MBB, const Container &BeforeSet, @@ -206,7 +206,7 @@ getLatestInsertPos(MachineBasicBlock *MBB, const Container &BeforeSet, while (InsertPos != MBB->end()) { if (AfterSet.count(&*InsertPos)) { #ifndef NDEBUG - // Sanity check + // Validation check for (auto Pos = InsertPos, E = MBB->end(); Pos != E; ++Pos) assert(!BeforeSet.count(&*Pos)); #endif diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp index 9ccbee819c35..3a0bef8c765c 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp @@ -68,7 +68,7 @@ bool LowerGlobalDtors::runOnModule(Module &M) { if (!InitList) return false; - // Sanity-check @llvm.global_dtor's type. + // Validate @llvm.global_dtor's type. auto *ETy = dyn_cast<StructType>(InitList->getType()->getElementType()); if (!ETy || ETy->getNumElements() != 3 || !ETy->getTypeAtIndex(0U)->isIntegerTy() || diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index f4a553365b02..8ce6b47d10e8 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -2657,7 +2657,7 @@ bool X86AsmParser::ParseATTOperand(OperandVector &Operands) { Expr = nullptr; Reg = RE->getRegNo(); - // Sanity check register. + // Check the register. if (Reg == X86::EIZ || Reg == X86::RIZ) return Error( Loc, "%eiz and %riz can only be used as index registers", @@ -2917,7 +2917,7 @@ bool X86AsmParser::ParseMemOperand(unsigned SegReg, const MCExpr *Disp, check(!isa<X86MCExpr>(E), BaseLoc, "expected register here")) return true; - // Sanity check register. + // Check the register. BaseReg = cast<X86MCExpr>(E)->getRegNo(); if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) return Error(BaseLoc, "eiz and riz can only be used as index registers", diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 84a24500dc79..828b4262b747 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6342,7 +6342,7 @@ static SDValue splitVectorIntUnary(SDValue Op, SelectionDAG &DAG) { /// Break a binary integer operation into 2 half sized ops and then /// concatenate the result back. static SDValue splitVectorIntBinary(SDValue Op, SelectionDAG &DAG) { - // Sanity check that all the types match. + // Assert that all the types match. EVT VT = Op.getValueType(); (void)VT; assert(Op.getOperand(0).getValueType() == VT && @@ -25424,7 +25424,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { } if (ArgMode == 2) { - // Sanity Check: Make sure using fp_offset makes sense. + // Make sure using fp_offset makes sense. assert(!Subtarget.useSoftFloat() && !(MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat)) && Subtarget.hasSSE1()); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index b7df3a40dd32..7c86262269fc 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -1315,7 +1315,7 @@ SDValue XCoreTargetLowering::LowerCCCArguments( CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1)); } } else { - // sanity check + // Only arguments passed on the stack should make it here. assert(VA.isMemLoc()); // Load the argument to a virtual register unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; |