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author | Craig Topper <craig.topper@sifive.com> | 2020-11-03 20:57:53 -0800 |
---|---|---|
committer | Craig Topper <craig.topper@sifive.com> | 2020-11-03 20:58:51 -0800 |
commit | d34152324d87fc9d9dbba5ffe7c8e383a9296e65 (patch) | |
tree | adeaba12eff528154999d98176fe085cd790fe33 | |
parent | 7ba3293691beb9a2c6ea4a81064c24580afe5816 (diff) | |
download | llvm-d34152324d87fc9d9dbba5ffe7c8e383a9296e65.tar.gz |
[RISCV] Add fshl with immediate tests for Zbt extension. NFC
We should be able to map this to fsri with adjustment of the
immediate.
-rw-r--r-- | llvm/test/CodeGen/RISCV/rv32Zbt.ll | 54 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rv64Zbt.ll | 51 |
2 files changed, 105 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbt.ll b/llvm/test/CodeGen/RISCV/rv32Zbt.ll index bb14a53c6e22..3de8d1dcf449 100644 --- a/llvm/test/CodeGen/RISCV/rv32Zbt.ll +++ b/llvm/test/CodeGen/RISCV/rv32Zbt.ll @@ -544,3 +544,57 @@ define i64 @fshri_i64(i64 %a, i64 %b) nounwind { %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5) ret i64 %1 } + +define i32 @fshli_i32(i32 %a, i32 %b) nounwind { +; RV32I-LABEL: fshli_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: srli a1, a1, 27 +; RV32I-NEXT: slli a0, a0, 5 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: fshli_i32: +; RV32IB: # %bb.0: +; RV32IB-NEXT: addi a2, zero, 5 +; RV32IB-NEXT: fsl a0, a0, a2, a1 +; RV32IB-NEXT: ret +; +; RV32IBT-LABEL: fshli_i32: +; RV32IBT: # %bb.0: +; RV32IBT-NEXT: addi a2, zero, 5 +; RV32IBT-NEXT: fsl a0, a0, a2, a1 +; RV32IBT-NEXT: ret + %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5) + ret i32 %1 +} + +define i64 @fshli_i64(i64 %a, i64 %b) nounwind { +; RV32I-LABEL: fshli_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: srli a2, a3, 27 +; RV32I-NEXT: slli a3, a0, 5 +; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: srli a0, a0, 27 +; RV32I-NEXT: slli a1, a1, 5 +; RV32I-NEXT: or a1, a1, a0 +; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: fshli_i64: +; RV32IB: # %bb.0: +; RV32IB-NEXT: addi a4, zero, 5 +; RV32IB-NEXT: fsl a2, a0, a4, a3 +; RV32IB-NEXT: fsl a1, a1, a4, a0 +; RV32IB-NEXT: mv a0, a2 +; RV32IB-NEXT: ret +; +; RV32IBT-LABEL: fshli_i64: +; RV32IBT: # %bb.0: +; RV32IBT-NEXT: addi a4, zero, 5 +; RV32IBT-NEXT: fsl a2, a0, a4, a3 +; RV32IBT-NEXT: fsl a1, a1, a4, a0 +; RV32IBT-NEXT: mv a0, a2 +; RV32IBT-NEXT: ret + %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5) + ret i64 %1 +} diff --git a/llvm/test/CodeGen/RISCV/rv64Zbt.ll b/llvm/test/CodeGen/RISCV/rv64Zbt.ll index dc736ade8071..bb8e4639f34e 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbt.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbt.ll @@ -250,3 +250,54 @@ define i64 @fshri_i64(i64 %a, i64 %b) nounwind { %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5) ret i64 %1 } + +define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind { +; RV64I-LABEL: fshli_i32: +; RV64I: # %bb.0: +; RV64I-NEXT: srliw a1, a1, 27 +; RV64I-NEXT: slli a0, a0, 5 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: fshli_i32: +; RV64IB: # %bb.0: +; RV64IB-NEXT: slli a1, a1, 32 +; RV64IB-NEXT: addi a2, zero, 5 +; RV64IB-NEXT: fsl a0, a0, a2, a1 +; RV64IB-NEXT: sext.w a0, a0 +; RV64IB-NEXT: ret +; +; RV64IBT-LABEL: fshli_i32: +; RV64IBT: # %bb.0: +; RV64IBT-NEXT: slli a1, a1, 32 +; RV64IBT-NEXT: addi a2, zero, 5 +; RV64IBT-NEXT: fsl a0, a0, a2, a1 +; RV64IBT-NEXT: sext.w a0, a0 +; RV64IBT-NEXT: ret + %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5) + ret i32 %1 +} + +define i64 @fshli_i64(i64 %a, i64 %b) nounwind { +; RV64I-LABEL: fshli_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: srli a1, a1, 59 +; RV64I-NEXT: slli a0, a0, 5 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: fshli_i64: +; RV64IB: # %bb.0: +; RV64IB-NEXT: addi a2, zero, 5 +; RV64IB-NEXT: fsl a0, a0, a2, a1 +; RV64IB-NEXT: ret +; +; RV64IBT-LABEL: fshli_i64: +; RV64IBT: # %bb.0: +; RV64IBT-NEXT: addi a2, zero, 5 +; RV64IBT-NEXT: fsl a0, a0, a2, a1 +; RV64IBT-NEXT: ret + %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5) + ret i64 %1 +} |