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| author | Craig Topper <craig.topper@sifive.com> | 2021-11-08 15:05:27 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-11-08 15:10:24 -0800 |
| commit | 376233113e254e47ea9624c770150c1e90bbce80 (patch) | |
| tree | e6ead0bf35dc0005f9161c6e024dfddaa18e2bb8 | |
| parent | 28a06a1b8795604403c5ac2fdd69e676050c27a2 (diff) | |
| download | llvm-376233113e254e47ea9624c770150c1e90bbce80.tar.gz | |
[RISCV] Use TargetConstant for CSR number for READ_CSR/WRITE_CSR.
This is consistent with what we do for other operands that are required
to be constants.
I don't think this results in any real changes. The pattern match
code for isel treats ConstantSDNode and TargetConstantSDNode the same.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9d8d11e8b980..9f5f3d25bca9 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5362,7 +5362,7 @@ SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op, const MVT XLenVT = Subtarget.getXLenVT(); SDLoc DL(Op); SDValue Chain = Op->getOperand(0); - SDValue SysRegNo = DAG.getConstant( + SDValue SysRegNo = DAG.getTargetConstant( RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other); SDValue RM = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo); @@ -5394,7 +5394,7 @@ SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op, SDLoc DL(Op); SDValue Chain = Op->getOperand(0); SDValue RMValue = Op->getOperand(1); - SDValue SysRegNo = DAG.getConstant( + SDValue SysRegNo = DAG.getTargetConstant( RISCVSysReg::lookupSysRegByName("FRM")->Encoding, DL, XLenVT); // Encoding used for rounding mode in RISCV differs from that used in |