Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC""

With new test file this time.

Original message

This new test covers both with and without the F extension enabled.

This shows that the fptosi/fptoui for double->i32 use a different
libcall depending on whether the F extension is enabled. If it's
not enabled we use the 'si' library call. If it is enabled we use 'di'.

2 files changed, 106 insertions, 59 deletions

diff --git a/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
new file mode 100644
index 000000000000..6346a2d03c34
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
@@ -0,0 +1,106 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IF %s
+
+; The test cases check that we use the si versions of the conversions from
+; double.
+
+define i32 @fp64_to_ui32(double %a) nounwind {
+; RV64I-LABEL: fp64_to_ui32:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    call __fixunsdfsi
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IF-LABEL: fp64_to_ui32:
+; RV64IF:       # %bb.0: # %entry
+; RV64IF-NEXT:    addi sp, sp, -16
+; RV64IF-NEXT:    sd ra, 8(sp)
+; RV64IF-NEXT:    call __fixunsdfdi
+; RV64IF-NEXT:    ld ra, 8(sp)
+; RV64IF-NEXT:    addi sp, sp, 16
+; RV64IF-NEXT:    ret
+entry:
+  %conv = fptoui double %a to i32
+  ret i32 %conv
+}
+
+define i32 @fp64_to_si32(double %a) nounwind {
+; RV64I-LABEL: fp64_to_si32:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    call __fixdfsi
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IF-LABEL: fp64_to_si32:
+; RV64IF:       # %bb.0: # %entry
+; RV64IF-NEXT:    addi sp, sp, -16
+; RV64IF-NEXT:    sd ra, 8(sp)
+; RV64IF-NEXT:    call __fixdfdi
+; RV64IF-NEXT:    ld ra, 8(sp)
+; RV64IF-NEXT:    addi sp, sp, 16
+; RV64IF-NEXT:    ret
+entry:
+  %conv = fptosi double %a to i32
+  ret i32 %conv
+}
+
+
+
+declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
+declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
+
+define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
+; RV64I-LABEL: strict_fp64_to_ui32:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    call __fixunsdfsi
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IF-LABEL: strict_fp64_to_ui32:
+; RV64IF:       # %bb.0: # %entry
+; RV64IF-NEXT:    addi sp, sp, -16
+; RV64IF-NEXT:    sd ra, 8(sp)
+; RV64IF-NEXT:    call __fixunsdfdi
+; RV64IF-NEXT:    ld ra, 8(sp)
+; RV64IF-NEXT:    addi sp, sp, 16
+; RV64IF-NEXT:    ret
+entry:
+  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
+  ret i32 %conv
+}
+
+define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
+; RV64I-LABEL: struct_fp64_to_si32:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    call __fixdfsi
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IF-LABEL: struct_fp64_to_si32:
+; RV64IF:       # %bb.0: # %entry
+; RV64IF-NEXT:    addi sp, sp, -16
+; RV64IF-NEXT:    sd ra, 8(sp)
+; RV64IF-NEXT:    call __fixdfdi
+; RV64IF-NEXT:    ld ra, 8(sp)
+; RV64IF-NEXT:    addi sp, sp, 16
+; RV64IF-NEXT:    ret
+entry:
+  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
+  ret i32 %conv
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
index 5888fc3157c3..1008f0ccf371 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
@@ -739,40 +739,10 @@ entry:
   ret i32 %conv
 }
 
-define i32 @fp64_to_ui32(double %a) nounwind {
-; RV64I-LABEL: fp64_to_ui32:
-; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    call __fixunsdfsi
-; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-entry:
-  %conv = fptoui double %a to i32
-  ret i32 %conv
-}
-
-define i32 @fp64_to_si32(double %a) nounwind {
-; RV64I-LABEL: fp64_to_si32:
-; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    call __fixdfsi
-; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-entry:
-  %conv = fptosi double %a to i32
-  ret i32 %conv
-}
-
 
 
 declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
 declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
-declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
-declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
 
 define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp {
 ; RV64I-LABEL: strict_fp32_to_ui32:
@@ -801,32 +771,3 @@ entry:
   %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")
   ret i32 %conv
 }
-
-define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
-; RV64I-LABEL: strict_fp64_to_ui32:
-; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    call __fixunsdfsi
-; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-entry:
-  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
-  ret i32 %conv
-}
-
-define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
-; RV64I-LABEL: struct_fp64_to_si32:
-; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    call __fixdfsi
-; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-entry:
-  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
-  ret i32 %conv
-}
-