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| author | Chen Zheng <czhengsz@cn.ibm.com> | 2021-04-09 03:21:24 -0400 |
|---|---|---|
| committer | Chen Zheng <czhengsz@cn.ibm.com> | 2021-04-09 03:38:39 -0400 |
| commit | 4b54345e4770df8d26a9e41fe90fda490d32123f (patch) | |
| tree | db9422f4e3901c84eba67204a3c6dd46bd9f5322 | |
| parent | 6169f1537c87be3d6caeb94ccd6d68a7be6e2502 (diff) | |
| download | llvm-4b54345e4770df8d26a9e41fe90fda490d32123f.tar.gz | |
[NFC][PowerPC] add test cases for reverse memory op transformation
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-shuffle-le-multiple-uses.ll | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vsx-shuffle-le-multiple-uses.ll b/llvm/test/CodeGen/PowerPC/vsx-shuffle-le-multiple-uses.ll new file mode 100644 index 000000000000..6fbe8694f82d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vsx-shuffle-le-multiple-uses.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +define <2 x double> @loadHasMultipleUses(<2 x double>* %p1, <2 x double>* %p2) { +; CHECK-LABEL: loadHasMultipleUses: +; CHECK: # %bb.0: +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: stxv 0, 0(4) +; CHECK-NEXT: lxvd2x 34, 0, 3 +; CHECK-NEXT: blr + %v1 = load <2 x double>, <2 x double>* %p1 + store <2 x double> %v1, <2 x double>* %p2, align 16 + %v2 = shufflevector <2 x double> %v1, <2 x double> %v1, <2 x i32> < i32 1, i32 0> + ret <2 x double> %v2 +} + +define <2 x double> @storeHasMultipleUses(<2 x double> %v, <2 x double>* %p) { +; CHECK-LABEL: storeHasMultipleUses: +; CHECK: # %bb.0: +; CHECK-NEXT: xxswapd 0, 34 +; CHECK-NEXT: addi 3, 5, 256 +; CHECK-NEXT: stxvd2x 34, 0, 3 +; CHECK-NEXT: xxlor 34, 0, 0 +; CHECK-NEXT: blr + %v1 = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> < i32 1, i32 0> + %addr = getelementptr inbounds <2 x double>, <2 x double>* %p, i64 16 + store <2 x double> %v1, <2 x double>* %addr, align 16 + %v2 = shufflevector <2 x double> %v, <2 x double> %v, <2 x i32> < i32 1, i32 2> + ret <2 x double> %v2 +} + |