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| author | eopXD <yueh.ting.chen@gmail.com> | 2023-01-19 02:07:07 -0800 |
|---|---|---|
| committer | Tobias Hieta <tobias@hieta.se> | 2023-02-05 21:10:40 +0100 |
| commit | eeb925af77826dc36375e9a19f87f8167fb3b08c (patch) | |
| tree | 78c48ce140570778d04d291de8a4df27b6ae0fb6 | |
| parent | 2b8bbad770c0bb7fa19a43dbf222a1c2e9a6cff9 (diff) | |
| download | llvm-eeb925af77826dc36375e9a19f87f8167fb3b08c.tar.gz | |
[Clang][Doc] Add release note for changes for the RVV intrinsics
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D142094
| -rw-r--r-- | clang/docs/ReleaseNotes.rst | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 136f47bd2884..dfe164756673 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -881,6 +881,17 @@ RISC-V Support in Clang take architecture extensions from ``-march`` if both are given. - An ABI mismatch between GCC and Clang that related to the sign/zero-extension of integer scalars was fixed. +- An overall simplification of the RISC-V Vector intrinsics are done. The + simplification is based on + `riscv-non-isa/rvv-intrinsic-doc#186 <https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/186>`_. +- Intrinsics of `vcompress` and `vmerge` have been adjusted to have interfaces + be aligned among `vvm`, `vxm` intrinsics. The adjustment is base on + `riscv-non-isa/rvv-intrinsic-doc#185 <https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/185>`_. +- All RISC-V Vector intrinsics now share a `__riscv_` prefix, based on the + naming convention defined by + `riscv-non-isa/riscv-c-api-doc#31 <https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31>`_. +- Note that the RISC-V Vector C intrinsics are still under development. The RVV + C Intrinsic Task Group is working towards a ratified v1.0. X86 Support in Clang -------------------- |