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| author | jacquesguan <jacquesguan@me.com> | 2021-07-22 11:40:31 +0800 |
|---|---|---|
| committer | jacquesguan <jacquesguan@me.com> | 2022-01-10 10:51:27 +0800 |
| commit | 6b8362eb8dc87be8977e3c1d3a7b2ff35a15898c (patch) | |
| tree | feb82157a1cb5d4b132f7843a7a7253bf95bbe8c | |
| parent | 6fab2742758197949d7bc624f453e544129709a3 (diff) | |
| download | llvm-6b8362eb8dc87be8977e3c1d3a7b2ff35a15898c.tar.gz | |
[RISCV] Disable EEW=64 for index values when XLEN=32.
Disable EEW=64 for vector index load/store when XLEN=32.
Differential Revision: https://reviews.llvm.org/D106518
18 files changed, 1579 insertions, 5649 deletions
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index cc242da7f1ca..03e16be96abe 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -216,7 +216,7 @@ class RVVBuiltin<string suffix, string prototype, string type_range, string HeaderCode = ""; // Sub extension of vector spec. Currently only support Zvlsseg. - string RequiredExtension = ""; + list<string> RequiredExtensions = []; // Number of fields for Zvlsseg. int NF = 1; @@ -707,7 +707,7 @@ multiclass RVVIndexedLoad<string op> { Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); }] in { foreach type = TypeList in { - foreach eew_list = EEWList in { + foreach eew_list = EEWList[0-2] in { defvar eew = eew_list[0]; defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in { @@ -717,6 +717,15 @@ multiclass RVVIndexedLoad<string op> { } } } + defvar eew64 = "64"; + defvar eew64_type = "(Log2EEW:6)"; + let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask", + RequiredExtensions = ["RV64"] in { + def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>; + if !not(IsFloat<type>.val) then { + def: RVVBuiltin<"Uv", "UvPCUe" # eew64_type # "Uv", type>; + } + } } } } @@ -797,7 +806,7 @@ multiclass RVVIndexedStore<string op> { IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[4]->getType()}; }] in { foreach type = TypeList in { - foreach eew_list = EEWList in { + foreach eew_list = EEWList[0-2] in { defvar eew = eew_list[0]; defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in { @@ -807,6 +816,15 @@ multiclass RVVIndexedStore<string op> { } } } + defvar eew64 = "64"; + defvar eew64_type = "(Log2EEW:6)"; + let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask", + RequiredExtensions = ["RV64"] in { + def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>; + if !not(IsFloat<type>.val) then { + def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>; + } + } } } } @@ -1549,7 +1567,7 @@ defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>; defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>; // 7.8 Vector Load/Store Segment Instructions -let RequiredExtension = "Zvlsseg" in { +let RequiredExtensions = ["Zvlsseg"] in { defm : RVVUnitStridedSegLoad<"vlseg">; defm : RVVUnitStridedSegLoadFF<"vlseg">; defm : RVVStridedSegLoad<"vlsseg">; diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 62eef830318f..08724fb35397 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -141,6 +141,7 @@ enum RISCVExtension : uint8_t { D = 1 << 2, Zfh = 1 << 3, Zvlsseg = 1 << 4, + RV64 = 1 << 5, }; // TODO refactor RVVIntrinsic class design after support all intrinsic @@ -174,7 +175,7 @@ public: bool HasNoMaskedOverloaded, bool HasAutoDef, StringRef ManualCodegen, const RVVTypes &Types, const std::vector<int64_t> &IntrinsicTypes, - StringRef RequiredExtension, unsigned NF); + const std::vector<StringRef> &RequiredExtensions, unsigned NF); ~RVVIntrinsic() = default; StringRef getBuiltinName() const { return BuiltinName; } @@ -764,7 +765,8 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, bool HasNoMaskedOverloaded, bool HasAutoDef, StringRef ManualCodegen, const RVVTypes &OutInTypes, const std::vector<int64_t> &NewIntrinsicTypes, - StringRef RequiredExtension, unsigned NF) + const std::vector<StringRef> &RequiredExtensions, + unsigned NF) : IRName(IRName), IsMask(IsMask), HasVL(HasVL), HasPolicy(HasPolicy), HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef), ManualCodegen(ManualCodegen.str()), NF(NF) { @@ -794,8 +796,12 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, else if (T->isFloatVector(64) || T->isFloat(64)) RISCVExtensions |= RISCVExtension::D; } - if (RequiredExtension == "Zvlsseg") - RISCVExtensions |= RISCVExtension::Zvlsseg; + for (auto Extension : RequiredExtensions) { + if (Extension == "Zvlsseg") + RISCVExtensions |= RISCVExtension::Zvlsseg; + if (Extension == "RV64") + RISCVExtensions |= RISCVExtension::RV64; + } // Init OutputType and InputTypes OutputType = OutInTypes[0]; @@ -1141,7 +1147,8 @@ void RVVEmitter::createRVVIntrinsics( StringRef ManualCodegenMask = R->getValueAsString("ManualCodegenMask"); std::vector<int64_t> IntrinsicTypes = R->getValueAsListOfInts("IntrinsicTypes"); - StringRef RequiredExtension = R->getValueAsString("RequiredExtension"); + std::vector<StringRef> RequiredExtensions = + R->getValueAsListOfStrings("RequiredExtensions"); StringRef IRName = R->getValueAsString("IRName"); StringRef IRNameMask = R->getValueAsString("IRNameMask"); unsigned NF = R->getValueAsInt("NF"); @@ -1209,7 +1216,7 @@ void RVVEmitter::createRVVIntrinsics( Name, SuffixStr, MangledName, MangledSuffixStr, IRName, /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL, HasPolicy, HasNoMaskedOverloaded, HasAutoDef, ManualCodegen, Types.getValue(), - IntrinsicTypes, RequiredExtension, NF)); + IntrinsicTypes, RequiredExtensions, NF)); if (HasMask) { // Create a mask intrinsic Optional<RVVTypes> MaskTypes = @@ -1218,7 +1225,7 @@ void RVVEmitter::createRVVIntrinsics( Name, SuffixStr, MangledName, MangledSuffixStr, IRNameMask, /*IsMask=*/true, HasMaskedOffOperand, HasVL, HasPolicy, HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask, - MaskTypes.getValue(), IntrinsicTypes, RequiredExtension, NF)); + MaskTypes.getValue(), IntrinsicTypes, RequiredExtensions, NF)); } } // end for Log2LMULList } // end for TypeRange @@ -1306,6 +1313,8 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) { OS << LS << "defined(__riscv_zfh)"; if (Extents & RISCVExtension::Zvlsseg) OS << LS << "defined(__riscv_zvlsseg)"; + if (Extents & RISCVExtension::RV64) + OS << LS << "(__riscv_xlen == 64)"; OS << "\n"; return true; } diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index dba693239430..b87a25278922 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -397,6 +397,10 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked, RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); + if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { + report_fatal_error("The V extension does not support EEW=64 for index " + "values when XLEN=32"); + } const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), static_cast<unsigned>(IndexLMUL)); @@ -475,6 +479,10 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked, RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); + if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { + report_fatal_error("The V extension does not support EEW=64 for index " + "values when XLEN=32"); + } const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo( NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), static_cast<unsigned>(IndexLMUL)); @@ -1128,6 +1136,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); + if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { + report_fatal_error("The V extension does not support EEW=64 for index " + "values when XLEN=32"); + } const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo( IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), static_cast<unsigned>(IndexLMUL)); @@ -1318,6 +1330,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); + if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { + report_fatal_error("The V extension does not support EEW=64 for index " + "values when XLEN=32"); + } const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo( IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), static_cast<unsigned>(IndexLMUL)); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 717c7a89a01b..71cad74de778 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5538,6 +5538,11 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op, } } + if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) { + IndexVT = IndexVT.changeVectorElementType(XLenVT); + Index = DAG.getNode(ISD::TRUNCATE, DL, IndexVT, Index); + } + if (!VL) VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; @@ -5639,6 +5644,11 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op, } } + if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) { + IndexVT = IndexVT.changeVectorElementType(XLenVT); + Index = DAG.getNode(ISD::TRUNCATE, DL, IndexVT, Index); + } + if (!VL) VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index e327afce0aad..ffa2f6a0c1a8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -801,6 +801,10 @@ foreach eew = [8, 16, 32, 64] in { // Vector Strided Instructions def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSched<eew>; def VSSE#eew#_V : VStridedStore<w, "vsse"#eew#".v">, VSSSched<eew>; +} + +foreach eew = [8, 16, 32] in { + defvar w = !cast<RISCVWidth>("LSWidth" # eew); // Vector Indexed Instructions def VLUXEI#eew#_V : @@ -812,7 +816,21 @@ foreach eew = [8, 16, 32, 64] in { def VSOXEI#eew#_V : VIndexedStore<MOPSTIndexedOrder, w, "vsoxei"#eew#".v">, VSXSched<eew, "O">; } +} // Predicates = [HasStdExtV] +let Predicates = [HasStdExtV, IsRV64] in { + // Vector Indexed Instructions + def VLUXEI64_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth64, "vluxei64.v">, + VLXSched<64, "U">; + def VLOXEI64_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth64, "vloxei64.v">, + VLXSched<64, "O">; + def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">, + VSXSched<64, "U">; + def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">, + VSXSched<64, "O">; +} // Predicates = [HasStdExtV, IsRV64] + +let Predicates = [HasStdExtV] in { def VLM_V : VUnitStrideLoadMask<"vlm.v">, Sched<[WriteVLDM, ReadVLDX]>; def VSM_V : VUnitStrideStoreMask<"vsm.v">, @@ -1430,6 +1448,10 @@ let Predicates = [HasStdExtZvlsseg] in { VStridedSegmentLoad<!add(nf, -1), w, "vlsseg"#nf#"e"#eew#".v">; def VSSSEG#nf#E#eew#_V : VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">; + } + + foreach eew = [8, 16, 32] in { + defvar w = !cast<RISCVWidth>("LSWidth"#eew); // Vector Indexed Instructions def VLUXSEG#nf#EI#eew#_V : @@ -1448,4 +1470,22 @@ let Predicates = [HasStdExtZvlsseg] in { } } // Predicates = [HasStdExtZvlsseg] +let Predicates = [HasStdExtZvlsseg, IsRV64] in { + foreach nf=2-8 in { + // Vector Indexed Instructions + def VLUXSEG#nf#EI64_V : + VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64, + "vluxseg"#nf#"ei64.v">; + def VLOXSEG#nf#EI64_V : + VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64, + "vloxseg"#nf#"ei64.v">; + def VSUXSEG#nf#EI64_V : + VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64, + "vsuxseg"#nf#"ei64.v">; + def VSOXSEG#nf#EI64_V : + VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64, + "vsoxseg"#nf#"ei64.v">; + } +} // Predicates = [HasStdExtZvlsseg, IsRV64] + include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index 91c7d1ac64a3..f97484f9c1d8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -1036,7 +1036,10 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1060,7 +1063,10 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1108,7 +1114,10 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1132,7 +1141,10 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1179,7 +1191,10 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1203,7 +1218,10 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1226,7 +1244,10 @@ define <8 x i64> @mgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsll.vi v8, v8, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1885,7 +1906,10 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %id ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1909,7 +1933,10 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %id ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1957,7 +1984,10 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> % ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -1981,7 +2011,10 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> % ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -2028,7 +2061,10 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> % ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -2052,7 +2088,10 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> % ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vsll.vi v8, v16, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -2075,7 +2114,10 @@ define <8 x double> @mgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsll.vi v8, v8, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll index 8ab646ae11c7..22d9c02ee8cb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -842,7 +842,10 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf8 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i64: @@ -864,7 +867,10 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf8 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i64: @@ -908,7 +914,10 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf4 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i64: @@ -930,7 +939,10 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf4 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i64: @@ -973,7 +985,10 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf2 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8i64: @@ -995,7 +1010,10 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf2 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8i64: @@ -1016,7 +1034,10 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsll.vi v12, v12, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i64: @@ -1615,7 +1636,10 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf8 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f64: @@ -1637,7 +1661,10 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf8 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f64: @@ -1681,7 +1708,10 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf4 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f64: @@ -1703,7 +1733,10 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf4 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f64: @@ -1746,7 +1779,10 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsext.vf2 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8f64: @@ -1768,7 +1804,10 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vzext.vf2 v16, v12 ; RV32-NEXT: vsll.vi v12, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8f64: @@ -1789,7 +1828,10 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsll.vi v12, v12, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f64: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll index dcec41a63905..2d9b97c8f6b3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*>, <2 x i1>, i32) @@ -871,14 +871,25 @@ define <8 x i64> @vpgather_baseidx_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i } define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_v8i8_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf8 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -886,14 +897,25 @@ define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, < } define <8 x i64> @vpgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_v8i8_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf8 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -924,14 +946,25 @@ define <8 x i64> @vpgather_baseidx_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x } define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_v8i16_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -939,14 +972,25 @@ define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, } define <8 x i64> @vpgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_v8i16_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -976,14 +1020,25 @@ define <8 x i64> @vpgather_baseidx_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x } define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_v8i32_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -991,14 +1046,25 @@ define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, } define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_v8i32_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1006,13 +1072,23 @@ define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, } define <8 x i64> @vpgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v8, v8, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsll.vi v8, v8, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsll.vi v8, v8, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x i64> %v @@ -1532,14 +1608,25 @@ define <8 x double> @vpgather_baseidx_v8i8_v8f64(double* %base, <8 x i8> %idxs, } define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_v8i8_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf8 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1547,14 +1634,25 @@ define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %i } define <8 x double> @vpgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_v8i8_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf8 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1585,14 +1683,25 @@ define <8 x double> @vpgather_baseidx_v8i16_v8f64(double* %base, <8 x i16> %idxs } define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_v8i16_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1600,14 +1709,25 @@ define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> } define <8 x double> @vpgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_v8i16_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1637,14 +1757,25 @@ define <8 x double> @vpgather_baseidx_v8i32_v8f64(double* %base, <8 x i32> %idxs } define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_v8i32_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1652,14 +1783,25 @@ define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> } define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_v8i32_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v12, v8 -; CHECK-NEXT: vsll.vi v8, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1667,13 +1809,23 @@ define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> } define <8 x double> @vpgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v8, v8, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsll.vi v8, v8, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v12, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsll.vi v8, v8, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x double> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll index 52887d7a88d5..78024f3a029e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -riscv-v-vector-bits-min=128 \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8>, <2 x i8*>, <2 x i1>, i32) @@ -737,14 +737,25 @@ define void @vpscatter_baseidx_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> % } define void @vpscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_v8i8_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -752,14 +763,25 @@ define void @vpscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x } define void @vpscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_v8i8_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -790,14 +812,25 @@ define void @vpscatter_baseidx_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> } define void @vpscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_v8i16_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -805,14 +838,25 @@ define void @vpscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x } define void @vpscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_v8i16_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -842,14 +886,25 @@ define void @vpscatter_baseidx_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> } define void @vpscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_v8i32_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_v8i32_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_v8i32_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -857,14 +912,25 @@ define void @vpscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x } define void @vpscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_v8i32_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_v8i32_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_v8i32_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -872,13 +938,23 @@ define void @vpscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x } define void @vpscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_v8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v12, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsll.vi v12, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsll.vi v12, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) ret void @@ -1382,14 +1458,25 @@ define void @vpscatter_baseidx_v8i8_v8f64(<8 x double> %val, double* %base, <8 x } define void @vpscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_v8i8_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1397,14 +1484,25 @@ define void @vpscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, } define void @vpscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_v8i8_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1435,14 +1533,25 @@ define void @vpscatter_baseidx_v8i16_v8f64(<8 x double> %val, double* %base, <8 } define void @vpscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_v8i16_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1450,14 +1559,25 @@ define void @vpscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base } define void @vpscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_v8i16_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1487,14 +1607,25 @@ define void @vpscatter_baseidx_v8i32_v8f64(<8 x double> %val, double* %base, <8 } define void @vpscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_v8i32_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_v8i32_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_v8i32_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1502,14 +1633,25 @@ define void @vpscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base } define void @vpscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_v8i32_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v16, v12 -; CHECK-NEXT: vsll.vi v12, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_v8i32_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_v8i32_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vzext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1517,13 +1659,23 @@ define void @vpscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base } define void @vpscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_v8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v12, v12, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_v8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV32-NEXT: vsll.vi v12, v12, 3 +; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu +; RV32-NEXT: vnsrl.wi v16, v12, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_v8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vsll.vi v12, v12, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll index ceab47d6bada..1dd6fdc7fc52 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll @@ -1042,7 +1042,10 @@ define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vsca ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf8 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1066,7 +1069,10 @@ define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i8_nxv8i64(i64* %base, <vsca ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf8 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1114,7 +1120,10 @@ define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vsc ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf4 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1138,7 +1147,10 @@ define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i16_nxv8i64(i64* %base, <vsc ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf4 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1185,7 +1197,10 @@ define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vsc ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf2 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1209,7 +1224,10 @@ define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vsc ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf2 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1232,7 +1250,10 @@ define <vscale x 8 x i64> @mgather_baseidx_nxv8i64(i64* %base, <vscale x 8 x i64 ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsll.vi v8, v8, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1957,7 +1978,10 @@ define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i8_nxv8f64(double* %base, ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf8 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -1981,7 +2005,10 @@ define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i8_nxv8f64(double* %base, ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf8 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -2029,7 +2056,10 @@ define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i16_nxv8f64(double* %base ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf4 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -2053,7 +2083,10 @@ define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i16_nxv8f64(double* %base ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf4 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -2100,7 +2133,10 @@ define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i32_nxv8f64(double* %base ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf2 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -2124,7 +2160,10 @@ define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i32_nxv8f64(double* %base ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf2 v24, v8 ; RV32-NEXT: vsll.vi v8, v24, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -2147,7 +2186,10 @@ define <vscale x 8 x double> @mgather_baseidx_nxv8f64(double* %base, <vscale x 8 ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsll.vi v8, v8, 3 -; RV32-NEXT: vluxei64.v v16, (a0), v8, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll index 1301eb9ce74c..f2e36bc024af 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll @@ -842,7 +842,10 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i64: @@ -864,7 +867,10 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i64: @@ -908,7 +914,10 @@ define void @mscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i64: @@ -930,7 +939,10 @@ define void @mscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i64: @@ -973,7 +985,10 @@ define void @mscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8i64: @@ -995,7 +1010,10 @@ define void @mscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8i64: @@ -1016,7 +1034,10 @@ define void @mscatter_baseidx_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vsca ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsll.vi v16, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i64: @@ -1615,7 +1636,10 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, do ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f64: @@ -1637,7 +1661,10 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, do ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f64: @@ -1681,7 +1708,10 @@ define void @mscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, d ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f64: @@ -1703,7 +1733,10 @@ define void @mscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, d ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f64: @@ -1746,7 +1779,10 @@ define void @mscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, d ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8f64: @@ -1768,7 +1804,10 @@ define void @mscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, d ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vsll.vi v16, v24, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8f64: @@ -1789,7 +1828,10 @@ define void @mscatter_baseidx_nxv8f64(<vscale x 8 x double> %val, double* %base, ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsll.vi v16, v16, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8f64: diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll index ee41b7684b48..d1d84acbbb2d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll @@ -1,1285 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64( - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vloxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64( - <vscale x 1 x i8>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i8> %a -} - -declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8>, - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i8> @intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8> %0, - <vscale x 1 x i8>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i8> %a -} - -declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64( - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vloxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64( - <vscale x 2 x i8>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i8> %a -} - -declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8>, - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i8> @intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8> %0, - <vscale x 2 x i8>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i8> %a -} - -declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64( - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64( - <vscale x 4 x i8>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i8> %a -} - -declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8>, - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i8> @intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8> %0, - <vscale x 4 x i8>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i8> %a -} - -declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64( - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64( - <vscale x 8 x i8>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i8> %a -} - -declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8>, - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i8> @intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8> %0, - <vscale x 8 x i8>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i8> %a -} - -declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64( - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vloxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64( - <vscale x 1 x i16>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i16> %a -} - -declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16>, - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i16> @intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16> %0, - <vscale x 1 x i16>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i16> %a -} - -declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64( - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64( - <vscale x 2 x i16>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i16> %a -} - -declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16>, - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i16> @intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16> %0, - <vscale x 2 x i16>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i16> %a -} - -declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64( - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vloxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64( - <vscale x 4 x i16>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i16> %a -} - -declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16>, - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i16> @intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16> %0, - <vscale x 4 x i16>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i16> %a -} - -declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64( - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64( - <vscale x 8 x i16>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i16> %a -} - -declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16>, - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i16> @intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16> %0, - <vscale x 8 x i16>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i16> %a -} - -declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64( - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64( - <vscale x 1 x i32>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i32> %a -} - -declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32>, - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32> %0, - <vscale x 1 x i32>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i32> %a -} - -declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64( - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vloxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64( - <vscale x 2 x i32>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i32> %a -} - -declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32>, - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i32> @intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32> %0, - <vscale x 2 x i32>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i32> %a -} - -declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64( - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vloxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64( - <vscale x 4 x i32>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i32> %a -} - -declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32>, - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i32> @intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32> %0, - <vscale x 4 x i32>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i32> %a -} - -declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64( - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64( - <vscale x 8 x i32>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i32> %a -} - -declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32>, - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i32> @intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32> %0, - <vscale x 8 x i32>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i32> %a -} - -declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64( - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64( - <vscale x 1 x i64>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i64> %a -} - -declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64>, - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64> %0, - <vscale x 1 x i64>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i64> %a -} - -declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64( - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64( - <vscale x 2 x i64>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i64> %a -} - -declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64>, - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i64> @intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64> %0, - <vscale x 2 x i64>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i64> %a -} - -declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64( - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64( - <vscale x 4 x i64>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i64> %a -} - -declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64>, - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i64> @intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64> %0, - <vscale x 4 x i64>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i64> %a -} - -declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64( - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64( - <vscale x 8 x i64>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i64> %a -} - -declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64>, - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i64> @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64> %0, - <vscale x 8 x i64>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i64> %a -} - -declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64( - <vscale x 1 x half>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vloxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64( - <vscale x 1 x half>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x half> %a -} - -declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half>, - <vscale x 1 x half>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x half> @intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half> %0, - <vscale x 1 x half>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x half> %a -} - -declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64( - <vscale x 2 x half>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64( - <vscale x 2 x half>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x half> %a -} - -declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half>, - <vscale x 2 x half>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x half> @intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half> %0, - <vscale x 2 x half>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x half> %a -} - -declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64( - <vscale x 4 x half>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vloxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64( - <vscale x 4 x half>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x half> %a -} - -declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half>, - <vscale x 4 x half>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x half> @intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half> %0, - <vscale x 4 x half>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x half> %a -} - -declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64( - <vscale x 8 x half>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64( - <vscale x 8 x half>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x half> %a -} - -declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half>, - <vscale x 8 x half>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x half> @intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half> %0, - <vscale x 8 x half>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x half> %a -} - -declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64( - <vscale x 1 x float>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64( - <vscale x 1 x float>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x float> %a -} - -declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float>, - <vscale x 1 x float>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x float> @intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float> %0, - <vscale x 1 x float>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x float> %a -} - -declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64( - <vscale x 2 x float>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vloxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64( - <vscale x 2 x float>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x float> %a -} - -declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float>, - <vscale x 2 x float>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x float> @intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float> %0, - <vscale x 2 x float>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x float> %a -} - -declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64( - <vscale x 4 x float>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vloxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64( - <vscale x 4 x float>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x float> %a -} - -declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float>, - <vscale x 4 x float>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x float> @intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float> %0, - <vscale x 4 x float>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x float> %a -} - -declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64( - <vscale x 8 x float>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64( - <vscale x 8 x float>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x float> %a -} - -declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float>, - <vscale x 8 x float>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x float> @intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float> %0, - <vscale x 8 x float>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x float> %a -} - -declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64( - <vscale x 1 x double>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64( - <vscale x 1 x double>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x double> %a -} - -declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double>, - <vscale x 1 x double>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x double> @intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double> %0, - <vscale x 1 x double>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x double> %a -} - -declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64( - <vscale x 2 x double>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64( - <vscale x 2 x double>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x double> %a -} - -declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double>, - <vscale x 2 x double>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x double> @intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double> %0, - <vscale x 2 x double>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x double> %a -} - -declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64( - <vscale x 4 x double>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64( - <vscale x 4 x double>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x double> %a -} - -declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double>, - <vscale x 4 x double>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x double> @intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double> %0, - <vscale x 4 x double>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x double> %a -} - -declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64( - <vscale x 8 x double>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64( - <vscale x 8 x double>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x double> %a -} - -declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double>, - <vscale x 8 x double>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x double> @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double> %0, - <vscale x 8 x double>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x double> %a -} declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32( <vscale x 1 x i8>*, diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll index e20832d0a96e..9ab2d9ec0bc0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll @@ -1,1285 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64( - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vluxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64( - <vscale x 1 x i8>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i8> %a -} - -declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8>, - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8> %0, - <vscale x 1 x i8>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i8> %a -} - -declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64( - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vluxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64( - <vscale x 2 x i8>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i8> %a -} - -declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8>, - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8> %0, - <vscale x 2 x i8>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i8> %a -} - -declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64( - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64( - <vscale x 4 x i8>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i8> %a -} - -declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8>, - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8> %0, - <vscale x 4 x i8>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i8> %a -} - -declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64( - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vluxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64( - <vscale x 8 x i8>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i8> %a -} - -declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8>, - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8> %0, - <vscale x 8 x i8>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i8> %a -} - -declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64( - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vluxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64( - <vscale x 1 x i16>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i16> %a -} - -declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16>, - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16> %0, - <vscale x 1 x i16>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i16> %a -} - -declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64( - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64( - <vscale x 2 x i16>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i16> %a -} - -declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16>, - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16> %0, - <vscale x 2 x i16>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i16> %a -} - -declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64( - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vluxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64( - <vscale x 4 x i16>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i16> %a -} - -declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16>, - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16> %0, - <vscale x 4 x i16>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i16> %a -} - -declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64( - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vluxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64( - <vscale x 8 x i16>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i16> %a -} - -declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16>, - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16> %0, - <vscale x 8 x i16>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i16> %a -} - -declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64( - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64( - <vscale x 1 x i32>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i32> %a -} - -declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32>, - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32> %0, - <vscale x 1 x i32>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i32> %a -} - -declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64( - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vluxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64( - <vscale x 2 x i32>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i32> %a -} - -declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32>, - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32> %0, - <vscale x 2 x i32>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i32> %a -} - -declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64( - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vluxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64( - <vscale x 4 x i32>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i32> %a -} - -declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32>, - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32> %0, - <vscale x 4 x i32>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i32> %a -} - -declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64( - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vluxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64( - <vscale x 8 x i32>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i32> %a -} - -declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32>, - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32> %0, - <vscale x 8 x i32>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i32> %a -} - -declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64( - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64( - <vscale x 1 x i64>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x i64> %a -} - -declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64>, - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64> %0, - <vscale x 1 x i64>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x i64> %a -} - -declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64( - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64( - <vscale x 2 x i64>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x i64> %a -} - -declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64>, - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64> %0, - <vscale x 2 x i64>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x i64> %a -} - -declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64( - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64( - <vscale x 4 x i64>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x i64> %a -} - -declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64>, - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64> %0, - <vscale x 4 x i64>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x i64> %a -} - -declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64( - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64( - <vscale x 8 x i64>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x i64> %a -} - -declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64>, - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64> %0, - <vscale x 8 x i64>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x i64> %a -} - -declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64( - <vscale x 1 x half>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vluxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64( - <vscale x 1 x half>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x half> %a -} - -declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half>, - <vscale x 1 x half>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half> %0, - <vscale x 1 x half>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x half> %a -} - -declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64( - <vscale x 2 x half>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64( - <vscale x 2 x half>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x half> %a -} - -declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half>, - <vscale x 2 x half>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half> %0, - <vscale x 2 x half>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x half> %a -} - -declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64( - <vscale x 4 x half>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vluxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64( - <vscale x 4 x half>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x half> %a -} - -declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half>, - <vscale x 4 x half>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half> %0, - <vscale x 4 x half>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x half> %a -} - -declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64( - <vscale x 8 x half>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vluxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64( - <vscale x 8 x half>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x half> %a -} - -declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half>, - <vscale x 8 x half>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half> %0, - <vscale x 8 x half>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x half> %a -} - -declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64( - <vscale x 1 x float>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v9, (a0), v8 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64( - <vscale x 1 x float>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x float> %a -} - -declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float>, - <vscale x 1 x float>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float> %0, - <vscale x 1 x float>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x float> %a -} - -declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64( - <vscale x 2 x float>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vluxei64.v v10, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v10 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64( - <vscale x 2 x float>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x float> %a -} - -declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float>, - <vscale x 2 x float>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float> %0, - <vscale x 2 x float>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x float> %a -} - -declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64( - <vscale x 4 x float>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vluxei64.v v12, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v12 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64( - <vscale x 4 x float>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x float> %a -} - -declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float>, - <vscale x 4 x float>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float> %0, - <vscale x 4 x float>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x float> %a -} - -declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64( - <vscale x 8 x float>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vluxei64.v v16, (a0), v8 -; CHECK-NEXT: vmv.v.v v8, v16 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64( - <vscale x 8 x float>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x float> %a -} - -declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float>, - <vscale x 8 x float>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float> %0, - <vscale x 8 x float>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x float> %a -} - -declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64( - <vscale x 1 x double>*, - <vscale x 1 x i64>, - i32); - -define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double>* %0, <vscale x 1 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64( - <vscale x 1 x double>* %0, - <vscale x 1 x i64> %1, - i32 %2) - - ret <vscale x 1 x double> %a -} - -declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double>, - <vscale x 1 x double>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32, - i32); - -define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double> %0, - <vscale x 1 x double>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 1 x double> %a -} - -declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64( - <vscale x 2 x double>*, - <vscale x 2 x i64>, - i32); - -define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double>* %0, <vscale x 2 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64( - <vscale x 2 x double>* %0, - <vscale x 2 x i64> %1, - i32 %2) - - ret <vscale x 2 x double> %a -} - -declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double>, - <vscale x 2 x double>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32, - i32); - -define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double> %0, - <vscale x 2 x double>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 2 x double> %a -} - -declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64( - <vscale x 4 x double>*, - <vscale x 4 x i64>, - i32); - -define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double>* %0, <vscale x 4 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64( - <vscale x 4 x double>* %0, - <vscale x 4 x i64> %1, - i32 %2) - - ret <vscale x 4 x double> %a -} - -declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double>, - <vscale x 4 x double>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32, - i32); - -define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double> %0, - <vscale x 4 x double>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 4 x double> %a -} - -declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64( - <vscale x 8 x double>*, - <vscale x 8 x i64>, - i32); - -define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double>* %0, <vscale x 8 x i64> %1, i32 %2) nounwind { -; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8 -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64( - <vscale x 8 x double>* %0, - <vscale x 8 x i64> %1, - i32 %2) - - ret <vscale x 8 x double> %a -} - -declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double>, - <vscale x 8 x double>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32, - i32); - -define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double> %0, - <vscale x 8 x double>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4, i32 1) - - ret <vscale x 8 x double> %a -} declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32( <vscale x 1 x i8>*, diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll index 8801440877ca..71c27389ff14 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0i8(<vscale x 1 x i8*>, <vscale x 1 x i1>, i32) @@ -949,14 +949,25 @@ define <vscale x 8 x i64> @vpgather_baseidx_nxv8i8_nxv8i64(i64* %base, <vscale x } define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf8 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -964,14 +975,25 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vsc } define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf8 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1002,14 +1024,25 @@ define <vscale x 8 x i64> @vpgather_baseidx_nxv8i16_nxv8i64(i64* %base, <vscale } define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf4 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1017,14 +1050,25 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vs } define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf4 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1054,14 +1098,25 @@ define <vscale x 8 x i64> @vpgather_baseidx_nxv8i32_nxv8i64(i64* %base, <vscale } define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1069,14 +1124,25 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vs } define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1084,13 +1150,23 @@ define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vs } define <vscale x 8 x i64> @vpgather_baseidx_nxv8i64(i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsll.vi v8, v8, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsll.vi v8, v8, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsll.vi v8, v8, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %idxs %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) ret <vscale x 8 x i64> %v @@ -1668,14 +1744,25 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8i8_nxv8f64(double* %base, <vs } define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf8 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1683,14 +1770,25 @@ define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i8_nxv8f64(double* %base } define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf8 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1721,14 +1819,25 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8i16_nxv8f64(double* %base, <v } define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf4 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1736,14 +1845,25 @@ define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i16_nxv8f64(double* %bas } define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf4 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1773,14 +1893,25 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8i32_nxv8f64(double* %base, <v } define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1788,14 +1919,25 @@ define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i32_nxv8f64(double* %bas } define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v16, v8 -; CHECK-NEXT: vsll.vi v8, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1803,13 +1945,23 @@ define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i32_nxv8f64(double* %bas } define <vscale x 8 x double> @vpgather_baseidx_nxv8f64(double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpgather_baseidx_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsll.vi v8, v8, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpgather_baseidx_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsll.vi v8, v8, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v16, v8, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpgather_baseidx_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsll.vi v8, v8, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %idxs %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) ret <vscale x 8 x double> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll index c0db7f57a190..0f2a30ca260e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare void @llvm.vp.scatter.nxv1i8.nxv1p0i8(<vscale x 1 x i8>, <vscale x 1 x i8*>, <vscale x 1 x i1>, i32) @@ -809,14 +809,25 @@ define void @vpscatter_baseidx_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %bas } define void @vpscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf8 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf8 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf8 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -824,14 +835,25 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* } define void @vpscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf8 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf8 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf8 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -862,14 +884,25 @@ define void @vpscatter_baseidx_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %ba } define void @vpscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf4 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf4 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf4 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -877,14 +910,25 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64 } define void @vpscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf4 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf4 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf4 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -914,14 +958,25 @@ define void @vpscatter_baseidx_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %ba } define void @vpscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf2 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf2 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -929,14 +984,25 @@ define void @vpscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64 } define void @vpscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf2 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf2 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -944,13 +1010,23 @@ define void @vpscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64 } define void @vpscatter_baseidx_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_nxv8i64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsll.vi v16, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsll.vi v16, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsll.vi v16, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %idxs call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) ret void @@ -1508,14 +1584,25 @@ define void @vpscatter_baseidx_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double } define void @vpscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf8 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf8 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf8 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1523,14 +1610,25 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, d } define void @vpscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf8 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf8 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf8 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1561,14 +1659,25 @@ define void @vpscatter_baseidx_nxv8i16_nxv8f64(<vscale x 8 x double> %val, doubl } define void @vpscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf4 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf4 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf4 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1576,14 +1685,25 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, } define void @vpscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf4 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf4 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf4 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1613,14 +1733,25 @@ define void @vpscatter_baseidx_nxv8i32_nxv8f64(<vscale x 8 x double> %val, doubl } define void @vpscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsext.vf2 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsext.vf2 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1628,14 +1759,25 @@ define void @vpscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, } define void @vpscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v24, v16 -; CHECK-NEXT: vsll.vi v16, v24, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vzext.vf2 v24, v16 +; RV32-NEXT: vsll.vi v16, v24, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vzext.vf2 v24, v16 +; RV64-NEXT: vsll.vi v16, v24, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) @@ -1643,13 +1785,23 @@ define void @vpscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, } define void @vpscatter_baseidx_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vpscatter_baseidx_nxv8f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vsll.vi v16, v16, 3 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret +; RV32-LABEL: vpscatter_baseidx_nxv8f64: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV32-NEXT: vsll.vi v16, v16, 3 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu +; RV32-NEXT: vnsrl.wi v24, v16, 0 +; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vpscatter_baseidx_nxv8f64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu +; RV64-NEXT: vsll.vi v16, v16, 3 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t +; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %idxs call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll index e53679ba3059..81e63f9639d6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll @@ -1,1294 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -declare void @llvm.riscv.vsoxei.nxv1i8.nxv1i64( - <vscale x 1 x i8>, - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1i8.nxv1i64( - <vscale x 1 x i8> %0, - <vscale x 1 x i8>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8>, - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8> %0, - <vscale x 1 x i8>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2i8.nxv2i64( - <vscale x 2 x i8>, - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2i8.nxv2i64( - <vscale x 2 x i8> %0, - <vscale x 2 x i8>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8>, - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8> %0, - <vscale x 2 x i8>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4i8.nxv4i64( - <vscale x 4 x i8>, - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4i8.nxv4i64( - <vscale x 4 x i8> %0, - <vscale x 4 x i8>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8>, - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8> %0, - <vscale x 4 x i8>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8i8.nxv8i64( - <vscale x 8 x i8>, - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8i8.nxv8i64( - <vscale x 8 x i8> %0, - <vscale x 8 x i8>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8>, - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8> %0, - <vscale x 8 x i8>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv1i16.nxv1i64( - <vscale x 1 x i16>, - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1i16.nxv1i64( - <vscale x 1 x i16> %0, - <vscale x 1 x i16>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16>, - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16> %0, - <vscale x 1 x i16>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2i16.nxv2i64( - <vscale x 2 x i16>, - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2i16.nxv2i64( - <vscale x 2 x i16> %0, - <vscale x 2 x i16>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16>, - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16> %0, - <vscale x 2 x i16>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4i16.nxv4i64( - <vscale x 4 x i16>, - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4i16.nxv4i64( - <vscale x 4 x i16> %0, - <vscale x 4 x i16>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16>, - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16> %0, - <vscale x 4 x i16>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8i16.nxv8i64( - <vscale x 8 x i16>, - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8i16.nxv8i64( - <vscale x 8 x i16> %0, - <vscale x 8 x i16>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16>, - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16> %0, - <vscale x 8 x i16>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv1i32.nxv1i64( - <vscale x 1 x i32>, - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1i32.nxv1i64( - <vscale x 1 x i32> %0, - <vscale x 1 x i32>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32>, - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32> %0, - <vscale x 1 x i32>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2i32.nxv2i64( - <vscale x 2 x i32>, - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2i32.nxv2i64( - <vscale x 2 x i32> %0, - <vscale x 2 x i32>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32>, - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32> %0, - <vscale x 2 x i32>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4i32.nxv4i64( - <vscale x 4 x i32>, - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4i32.nxv4i64( - <vscale x 4 x i32> %0, - <vscale x 4 x i32>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32>, - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32> %0, - <vscale x 4 x i32>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8i32.nxv8i64( - <vscale x 8 x i32>, - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8i32.nxv8i64( - <vscale x 8 x i32> %0, - <vscale x 8 x i32>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32>, - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32> %0, - <vscale x 8 x i32>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv1i64.nxv1i64( - <vscale x 1 x i64>, - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1i64.nxv1i64( - <vscale x 1 x i64> %0, - <vscale x 1 x i64>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64>, - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64> %0, - <vscale x 1 x i64>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2i64.nxv2i64( - <vscale x 2 x i64>, - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2i64.nxv2i64( - <vscale x 2 x i64> %0, - <vscale x 2 x i64>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64>, - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64> %0, - <vscale x 2 x i64>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4i64.nxv4i64( - <vscale x 4 x i64>, - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4i64.nxv4i64( - <vscale x 4 x i64> %0, - <vscale x 4 x i64>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64>, - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64> %0, - <vscale x 4 x i64>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8i64.nxv8i64( - <vscale x 8 x i64>, - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8i64.nxv8i64( - <vscale x 8 x i64> %0, - <vscale x 8 x i64>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64>, - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64> %0, - <vscale x 8 x i64>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv1f16.nxv1i64( - <vscale x 1 x half>, - <vscale x 1 x half>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1f16.nxv1i64( - <vscale x 1 x half> %0, - <vscale x 1 x half>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half>, - <vscale x 1 x half>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half> %0, - <vscale x 1 x half>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2f16.nxv2i64( - <vscale x 2 x half>, - <vscale x 2 x half>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2f16.nxv2i64( - <vscale x 2 x half> %0, - <vscale x 2 x half>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half>, - <vscale x 2 x half>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half> %0, - <vscale x 2 x half>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4f16.nxv4i64( - <vscale x 4 x half>, - <vscale x 4 x half>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4f16.nxv4i64( - <vscale x 4 x half> %0, - <vscale x 4 x half>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half>, - <vscale x 4 x half>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half> %0, - <vscale x 4 x half>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8f16.nxv8i64( - <vscale x 8 x half>, - <vscale x 8 x half>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8f16.nxv8i64( - <vscale x 8 x half> %0, - <vscale x 8 x half>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half>, - <vscale x 8 x half>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half> %0, - <vscale x 8 x half>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv1f32.nxv1i64( - <vscale x 1 x float>, - <vscale x 1 x float>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1f32.nxv1i64( - <vscale x 1 x float> %0, - <vscale x 1 x float>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float>, - <vscale x 1 x float>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float> %0, - <vscale x 1 x float>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2f32.nxv2i64( - <vscale x 2 x float>, - <vscale x 2 x float>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2f32.nxv2i64( - <vscale x 2 x float> %0, - <vscale x 2 x float>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float>, - <vscale x 2 x float>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float> %0, - <vscale x 2 x float>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4f32.nxv4i64( - <vscale x 4 x float>, - <vscale x 4 x float>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4f32.nxv4i64( - <vscale x 4 x float> %0, - <vscale x 4 x float>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float>, - <vscale x 4 x float>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float> %0, - <vscale x 4 x float>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8f32.nxv8i64( - <vscale x 8 x float>, - <vscale x 8 x float>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8f32.nxv8i64( - <vscale x 8 x float> %0, - <vscale x 8 x float>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float>, - <vscale x 8 x float>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float> %0, - <vscale x 8 x float>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv1f64.nxv1i64( - <vscale x 1 x double>, - <vscale x 1 x double>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv1f64.nxv1i64( - <vscale x 1 x double> %0, - <vscale x 1 x double>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double>, - <vscale x 1 x double>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double> %0, - <vscale x 1 x double>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv2f64.nxv2i64( - <vscale x 2 x double>, - <vscale x 2 x double>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv2f64.nxv2i64( - <vscale x 2 x double> %0, - <vscale x 2 x double>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double>, - <vscale x 2 x double>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double> %0, - <vscale x 2 x double>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv4f64.nxv4i64( - <vscale x 4 x double>, - <vscale x 4 x double>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv4f64.nxv4i64( - <vscale x 4 x double> %0, - <vscale x 4 x double>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double>, - <vscale x 4 x double>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double> %0, - <vscale x 4 x double>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsoxei.nxv8f64.nxv8i64( - <vscale x 8 x double>, - <vscale x 8 x double>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.nxv8f64.nxv8i64( - <vscale x 8 x double> %0, - <vscale x 8 x double>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double>, - <vscale x 8 x double>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double> %0, - <vscale x 8 x double>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - declare void @llvm.riscv.vsoxei.nxv1i8.nxv1i32( <vscale x 1 x i8>, <vscale x 1 x i8>*, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll index 05c70dcfbed9..c80b0b0140bd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll @@ -1,1294 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -declare void @llvm.riscv.vsuxei.nxv1i8.nxv1i64( - <vscale x 1 x i8>, - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1i8.nxv1i64( - <vscale x 1 x i8> %0, - <vscale x 1 x i8>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8>, - <vscale x 1 x i8>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i64( - <vscale x 1 x i8> %0, - <vscale x 1 x i8>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2i8.nxv2i64( - <vscale x 2 x i8>, - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2i8.nxv2i64( - <vscale x 2 x i8> %0, - <vscale x 2 x i8>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8>, - <vscale x 2 x i8>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i64( - <vscale x 2 x i8> %0, - <vscale x 2 x i8>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4i8.nxv4i64( - <vscale x 4 x i8>, - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4i8.nxv4i64( - <vscale x 4 x i8> %0, - <vscale x 4 x i8>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8>, - <vscale x 4 x i8>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i64( - <vscale x 4 x i8> %0, - <vscale x 4 x i8>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8i8.nxv8i64( - <vscale x 8 x i8>, - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8i8.nxv8i64( - <vscale x 8 x i8> %0, - <vscale x 8 x i8>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8>, - <vscale x 8 x i8>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i64( - <vscale x 8 x i8> %0, - <vscale x 8 x i8>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv1i16.nxv1i64( - <vscale x 1 x i16>, - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1i16.nxv1i64( - <vscale x 1 x i16> %0, - <vscale x 1 x i16>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16>, - <vscale x 1 x i16>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i64( - <vscale x 1 x i16> %0, - <vscale x 1 x i16>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2i16.nxv2i64( - <vscale x 2 x i16>, - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2i16.nxv2i64( - <vscale x 2 x i16> %0, - <vscale x 2 x i16>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16>, - <vscale x 2 x i16>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i64( - <vscale x 2 x i16> %0, - <vscale x 2 x i16>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4i16.nxv4i64( - <vscale x 4 x i16>, - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4i16.nxv4i64( - <vscale x 4 x i16> %0, - <vscale x 4 x i16>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16>, - <vscale x 4 x i16>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i64( - <vscale x 4 x i16> %0, - <vscale x 4 x i16>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8i16.nxv8i64( - <vscale x 8 x i16>, - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8i16.nxv8i64( - <vscale x 8 x i16> %0, - <vscale x 8 x i16>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16>, - <vscale x 8 x i16>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i64( - <vscale x 8 x i16> %0, - <vscale x 8 x i16>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv1i32.nxv1i64( - <vscale x 1 x i32>, - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1i32.nxv1i64( - <vscale x 1 x i32> %0, - <vscale x 1 x i32>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32>, - <vscale x 1 x i32>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i64( - <vscale x 1 x i32> %0, - <vscale x 1 x i32>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2i32.nxv2i64( - <vscale x 2 x i32>, - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2i32.nxv2i64( - <vscale x 2 x i32> %0, - <vscale x 2 x i32>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32>, - <vscale x 2 x i32>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i64( - <vscale x 2 x i32> %0, - <vscale x 2 x i32>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4i32.nxv4i64( - <vscale x 4 x i32>, - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4i32.nxv4i64( - <vscale x 4 x i32> %0, - <vscale x 4 x i32>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32>, - <vscale x 4 x i32>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64( - <vscale x 4 x i32> %0, - <vscale x 4 x i32>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8i32.nxv8i64( - <vscale x 8 x i32>, - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8i32.nxv8i64( - <vscale x 8 x i32> %0, - <vscale x 8 x i32>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32>, - <vscale x 8 x i32>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i64( - <vscale x 8 x i32> %0, - <vscale x 8 x i32>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv1i64.nxv1i64( - <vscale x 1 x i64>, - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1i64.nxv1i64( - <vscale x 1 x i64> %0, - <vscale x 1 x i64>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64>, - <vscale x 1 x i64>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i64( - <vscale x 1 x i64> %0, - <vscale x 1 x i64>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2i64.nxv2i64( - <vscale x 2 x i64>, - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2i64.nxv2i64( - <vscale x 2 x i64> %0, - <vscale x 2 x i64>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64>, - <vscale x 2 x i64>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i64( - <vscale x 2 x i64> %0, - <vscale x 2 x i64>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4i64.nxv4i64( - <vscale x 4 x i64>, - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4i64.nxv4i64( - <vscale x 4 x i64> %0, - <vscale x 4 x i64>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64>, - <vscale x 4 x i64>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i64( - <vscale x 4 x i64> %0, - <vscale x 4 x i64>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8i64.nxv8i64( - <vscale x 8 x i64>, - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8i64.nxv8i64( - <vscale x 8 x i64> %0, - <vscale x 8 x i64>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64>, - <vscale x 8 x i64>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i64( - <vscale x 8 x i64> %0, - <vscale x 8 x i64>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv1f16.nxv1i64( - <vscale x 1 x half>, - <vscale x 1 x half>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1f16.nxv1i64( - <vscale x 1 x half> %0, - <vscale x 1 x half>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half>, - <vscale x 1 x half>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i64( - <vscale x 1 x half> %0, - <vscale x 1 x half>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2f16.nxv2i64( - <vscale x 2 x half>, - <vscale x 2 x half>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2f16.nxv2i64( - <vscale x 2 x half> %0, - <vscale x 2 x half>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half>, - <vscale x 2 x half>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i64( - <vscale x 2 x half> %0, - <vscale x 2 x half>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4f16.nxv4i64( - <vscale x 4 x half>, - <vscale x 4 x half>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4f16.nxv4i64( - <vscale x 4 x half> %0, - <vscale x 4 x half>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half>, - <vscale x 4 x half>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i64( - <vscale x 4 x half> %0, - <vscale x 4 x half>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8f16.nxv8i64( - <vscale x 8 x half>, - <vscale x 8 x half>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8f16.nxv8i64( - <vscale x 8 x half> %0, - <vscale x 8 x half>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half>, - <vscale x 8 x half>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i64( - <vscale x 8 x half> %0, - <vscale x 8 x half>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv1f32.nxv1i64( - <vscale x 1 x float>, - <vscale x 1 x float>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1f32.nxv1i64( - <vscale x 1 x float> %0, - <vscale x 1 x float>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float>, - <vscale x 1 x float>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i64( - <vscale x 1 x float> %0, - <vscale x 1 x float>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2f32.nxv2i64( - <vscale x 2 x float>, - <vscale x 2 x float>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2f32.nxv2i64( - <vscale x 2 x float> %0, - <vscale x 2 x float>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float>, - <vscale x 2 x float>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i64( - <vscale x 2 x float> %0, - <vscale x 2 x float>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4f32.nxv4i64( - <vscale x 4 x float>, - <vscale x 4 x float>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4f32.nxv4i64( - <vscale x 4 x float> %0, - <vscale x 4 x float>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float>, - <vscale x 4 x float>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i64( - <vscale x 4 x float> %0, - <vscale x 4 x float>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8f32.nxv8i64( - <vscale x 8 x float>, - <vscale x 8 x float>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8f32.nxv8i64( - <vscale x 8 x float> %0, - <vscale x 8 x float>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float>, - <vscale x 8 x float>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i64( - <vscale x 8 x float> %0, - <vscale x 8 x float>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv1f64.nxv1i64( - <vscale x 1 x double>, - <vscale x 1 x double>*, - <vscale x 1 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv1f64.nxv1i64( - <vscale x 1 x double> %0, - <vscale x 1 x double>* %1, - <vscale x 1 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double>, - <vscale x 1 x double>*, - <vscale x 1 x i64>, - <vscale x 1 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i64( - <vscale x 1 x double> %0, - <vscale x 1 x double>* %1, - <vscale x 1 x i64> %2, - <vscale x 1 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv2f64.nxv2i64( - <vscale x 2 x double>, - <vscale x 2 x double>*, - <vscale x 2 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv2f64.nxv2i64( - <vscale x 2 x double> %0, - <vscale x 2 x double>* %1, - <vscale x 2 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double>, - <vscale x 2 x double>*, - <vscale x 2 x i64>, - <vscale x 2 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i64( - <vscale x 2 x double> %0, - <vscale x 2 x double>* %1, - <vscale x 2 x i64> %2, - <vscale x 2 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv4f64.nxv4i64( - <vscale x 4 x double>, - <vscale x 4 x double>*, - <vscale x 4 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv4f64.nxv4i64( - <vscale x 4 x double> %0, - <vscale x 4 x double>* %1, - <vscale x 4 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double>, - <vscale x 4 x double>*, - <vscale x 4 x i64>, - <vscale x 4 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i64( - <vscale x 4 x double> %0, - <vscale x 4 x double>* %1, - <vscale x 4 x i64> %2, - <vscale x 4 x i1> %3, - i32 %4) - - ret void -} - -declare void @llvm.riscv.vsuxei.nxv8f64.nxv8i64( - <vscale x 8 x double>, - <vscale x 8 x double>*, - <vscale x 8 x i64>, - i32); - -define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16 -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.nxv8f64.nxv8i64( - <vscale x 8 x double> %0, - <vscale x 8 x double>* %1, - <vscale x 8 x i64> %2, - i32 %3) - - ret void -} - -declare void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double>, - <vscale x 8 x double>*, - <vscale x 8 x i64>, - <vscale x 8 x i1>, - i32); - -define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t -; CHECK-NEXT: ret -entry: - call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i64( - <vscale x 8 x double> %0, - <vscale x 8 x double>* %1, - <vscale x 8 x i64> %2, - <vscale x 8 x i1> %3, - i32 %4) - - ret void -} - declare void @llvm.riscv.vsuxei.nxv1i8.nxv1i32( <vscale x 1 x i8>, <vscale x 1 x i8>*, diff --git a/llvm/test/MC/RISCV/rvv/invalid-eew.s b/llvm/test/MC/RISCV/rvv/invalid-eew.s new file mode 100644 index 000000000000..62767ff95495 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/invalid-eew.s @@ -0,0 +1,195 @@ +# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-v \ +# RUN: --mattr=+experimental-zvlsseg %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vluxei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxei64.v v24, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxei64.v v24, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxei64.v v24, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxei64.v v24, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg2ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg2ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg3ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg3ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg4ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg4ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg5ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg5ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg6ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg6ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg7ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg7ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg8ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vluxseg8ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg2ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg2ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg3ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg3ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg4ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg4ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg5ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg5ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg6ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg6ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg7ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg7ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg8ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vloxseg8ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg2ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg2ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg3ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg3ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg4ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg4ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg5ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg5ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg6ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg6ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg7ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg7ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg8ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsuxseg8ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg2ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg2ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg3ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg3ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg4ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg4ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg5ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg5ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg6ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg6ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg7ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg7ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg8ei64.v v8, (a0), v4, v0.t +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set + +vsoxseg8ei64.v v8, (a0), v4 +# CHECK-ERROR: instruction requires the following: RV64I Base Instruction Set |