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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:18:32 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:20:01 +0300 |
| commit | df2b42d12e4b4ff18bec8460c3d6ede6b411c048 (patch) | |
| tree | cbda5da045bd37bef9a1e4f6cff0bc14af80a80b | |
| parent | 45caac91c4e0caf64ec933f35c4a2d86a3fa31e3 (diff) | |
| download | llvm-df2b42d12e4b4ff18bec8460c3d6ede6b411c048.tar.gz | |
[X86][Costmodel] Load/store i16 Stride=4 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/rnsf639Wh - for intels `Block RThroughput: =17.0`; for ryzens, `Block RThroughput: <=7.5`
So pick cost of `17`.
For store we have:
https://godbolt.org/z/565KKrcY6 - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =2.0`
So pick cost of `6`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110537
3 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 8cdfceb44d51..4d692359e484 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5086,6 +5086,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 + {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 }; @@ -5112,6 +5113,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) + {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) }; if (Opcode == Instruction::Load) { diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll index 363ba0a5808c..18c01263ca8e 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll @@ -10,7 +10,7 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK: LV: Checking a loop in "test" ; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i16, i16* %in0, align 2 ; CHECK: LV: Found an estimated cost of 7 for VF 2 For instruction: %v0 = load i16, i16* %in0, align 2 -; CHECK: LV: Found an estimated cost of 41 for VF 4 For instruction: %v0 = load i16, i16* %in0, align 2 +; CHECK: LV: Found an estimated cost of 18 for VF 4 For instruction: %v0 = load i16, i16* %in0, align 2 ; CHECK: LV: Found an estimated cost of 82 for VF 8 For instruction: %v0 = load i16, i16* %in0, align 2 ; CHECK: LV: Found an estimated cost of 228 for VF 16 For instruction: %v0 = load i16, i16* %in0, align 2 ; CHECK: LV: Found an estimated cost of 456 for VF 32 For instruction: %v0 = load i16, i16* %in0, align 2 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll index e0aaf683029d..047ac462a3b9 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll @@ -10,7 +10,7 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK: LV: Checking a loop in "test" ; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v3, i16* %out3, align 2 ; CHECK: LV: Found an estimated cost of 3 for VF 2 For instruction: store i16 %v3, i16* %out3, align 2 -; CHECK: LV: Found an estimated cost of 49 for VF 4 For instruction: store i16 %v3, i16* %out3, align 2 +; CHECK: LV: Found an estimated cost of 7 for VF 4 For instruction: store i16 %v3, i16* %out3, align 2 ; CHECK: LV: Found an estimated cost of 98 for VF 8 For instruction: store i16 %v3, i16* %out3, align 2 ; CHECK: LV: Found an estimated cost of 228 for VF 16 For instruction: store i16 %v3, i16* %out3, align 2 ; CHECK: LV: Found an estimated cost of 456 for VF 32 For instruction: store i16 %v3, i16* %out3, align 2 |