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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-12-13 22:16:46 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-12-14 15:36:32 +0000 |
| commit | a9d811405f887fbc438154047aaa7954ad99a19e (patch) | |
| tree | e3f0ba10541be38eb3a1d062701272c5081a2963 | |
| parent | f00da7c3bc8ea85aefe84fef6294541c11d2578e (diff) | |
| download | llvm-a9d811405f887fbc438154047aaa7954ad99a19e.tar.gz | |
[X86] combineOr - pull out repeated SDLoc(). NFCI.
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1c23f263fae1..64c91cb62c8a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -46646,11 +46646,12 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG, SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); EVT VT = N->getValueType(0); + SDLoc dl(N); // If this is SSE1 only convert to FOR to avoid scalarization. if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) { return DAG.getBitcast(MVT::v4i32, - DAG.getNode(X86ISD::FOR, SDLoc(N), MVT::v4f32, + DAG.getNode(X86ISD::FOR, dl, MVT::v4f32, DAG.getBitcast(MVT::v4f32, N0), DAG.getBitcast(MVT::v4f32, N1))); } @@ -46662,7 +46663,6 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG, SmallVector<APInt, 2> SrcPartials; if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps, &SrcPartials) && SrcOps.size() == 1) { - SDLoc dl(N); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements(); EVT MaskVT = EVT::getIntegerVT(*DAG.getContext(), NumElts); @@ -46709,7 +46709,6 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG, if (NumElts >= 16 && N1.getOpcode() == X86ISD::KSHIFTL && N1.getConstantOperandAPInt(1) == HalfElts && DAG.MaskedValueIsZero(N0, APInt(1, 1), UpperElts)) { - SDLoc dl(N); return DAG.getNode( ISD::CONCAT_VECTORS, dl, VT, extractSubVector(N0, 0, DAG, dl, HalfElts), @@ -46718,7 +46717,6 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG, if (NumElts >= 16 && N0.getOpcode() == X86ISD::KSHIFTL && N0.getConstantOperandAPInt(1) == HalfElts && DAG.MaskedValueIsZero(N1, APInt(1, 1), UpperElts)) { - SDLoc dl(N); return DAG.getNode( ISD::CONCAT_VECTORS, dl, VT, extractSubVector(N1, 0, DAG, dl, HalfElts), |