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| author | John Criswell <criswell@uiuc.edu> | 2004-08-09 21:34:34 +0000 |
|---|---|---|
| committer | John Criswell <criswell@uiuc.edu> | 2004-08-09 21:34:34 +0000 |
| commit | f0958ae6eb37afe15652302bb207f4300e698c11 (patch) | |
| tree | ec36c88af8a0ee771a2281a72deeb0514c4018d9 | |
| parent | 7ee0099de5e49ff4f7758fa441474b70e779b9cf (diff) | |
| download | llvm-f0958ae6eb37afe15652302bb207f4300e698c11.tar.gz | |
Merged in changes to the instruction combining pass.
llvm-svn: 15598
| -rw-r--r-- | llvm/lib/Transforms/Scalar/InstructionCombining.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp index eb4f1e31a6a1..bf0f0e839d00 100644 --- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp @@ -829,7 +829,7 @@ Instruction *InstCombiner::visitRem(BinaryOperator &I) { if (I.getType()->isSigned()) if (Value *RHSNeg = dyn_castNegVal(I.getOperand(1))) if (!isa<ConstantSInt>(RHSNeg) || - cast<ConstantSInt>(RHSNeg)->getValue() >= 0) { + cast<ConstantSInt>(RHSNeg)->getValue() > 0) { // X % -Y -> X % Y AddUsesToWorkList(I); I.setOperand(1, RHSNeg); |