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| author | Fraser Cormack <fraser@codeplay.com> | 2022-04-14 13:03:56 +0100 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2022-04-25 20:27:35 -0700 |
| commit | 21ce6cfd1d9357b54173d43e3d18960f487f6663 (patch) | |
| tree | fca04f27578b6a9c247c1eafbed3b955e8965644 | |
| parent | 58d5fbe2c20bbd2499675c2d7a35dc157c767fec (diff) | |
| download | llvm-21ce6cfd1d9357b54173d43e3d18960f487f6663.tar.gz | |
[RISCV] Add tests showing incorrect BUILD_VECTOR lowering
These tests both use vector constants misidentified as VID sequences.
Because the initial run of elements has a zero step, the elements are
skipped until such a step can be identified. The bug is that the skipped
elements are never validated, even though the computed step is
incompatible across the entire sequence.
A fix will follow in a subseqeuent patch.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123785
(cherry picked from commit 00537946aa29928894ba140687de1b6f9494e44d)
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 80c4ad8662b1..6fb669feb462 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -704,3 +704,24 @@ define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) { %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer ret <8 x i16> %splat } + +; FIXME: This is not a vid sequence! +define <4 x i8> @buildvec_not_vid_v4i8_1() { +; CHECK-LABEL: buildvec_not_vid_v4i8_1: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: ret + ret <4 x i8> <i8 0, i8 0, i8 2, i8 3> +} + +; FIXME: This is not a vid sequence! +define <4 x i8> @buildvec_not_vid_v4i8_2() { +; CHECK-LABEL: buildvec_not_vid_v4i8_2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vrsub.vi v8, v8, 3 +; CHECK-NEXT: ret + ret <4 x i8> <i8 3, i8 3, i8 1, i8 0> +} |