diff options
| author | Sanjay Patel <spatel@rotateright.com> | 2022-04-11 10:48:47 -0400 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2022-04-14 16:12:32 -0700 |
| commit | 5ea5e3c01b7be01c9a9689233b4ab3e8aa4dc7dc (patch) | |
| tree | 61f2cdc2eaadc91d34c812b61e7a8a460064f9d7 | |
| parent | fe8a27acd716a42667f5a572f52f2b04636010ff (diff) | |
| download | llvm-5ea5e3c01b7be01c9a9689233b4ab3e8aa4dc7dc.tar.gz | |
[InstCombine] add tests for low-mask of ashr; NFC
(cherry picked from commit 141892d481fcf446c9bf1ae5fb600d797295debc)
| -rw-r--r-- | llvm/test/Transforms/InstCombine/and.ll | 80 |
1 files changed, 72 insertions, 8 deletions
diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll index 53c7f09189ff..786535fe67e4 100644 --- a/llvm/test/Transforms/InstCombine/and.ll +++ b/llvm/test/Transforms/InstCombine/and.ll @@ -390,17 +390,81 @@ define i8 @test27(i8 %A) { ret i8 %E } -;; This is just a zero-extending shr. -define i32 @test28(i32 %X) { -; CHECK-LABEL: @test28( +;; No demand for extra sign bits. + +define i32 @ashr_lowmask(i32 %x) { +; CHECK-LABEL: @ashr_lowmask( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 24 ; CHECK-NEXT: ret i32 [[TMP1]] ; - ;; Sign extend - %Y = ashr i32 %X, 24 - ;; Mask out sign bits - %Z = and i32 %Y, 255 - ret i32 %Z + %a = ashr i32 %x, 24 + %r = and i32 %a, 255 + ret i32 %r +} + +define i32 @ashr_lowmask_use(i32 %x) { +; CHECK-LABEL: @ashr_lowmask_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 1 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 2147483647 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 1 + call void @use32(i32 %a) + %r = and i32 %a, 2147483647 + ret i32 %r +} + +define <2 x i8> @ashr_lowmask_use_splat(<2 x i8> %x, <2 x i8>* %p) { +; CHECK-LABEL: @ashr_lowmask_use_splat( +; CHECK-NEXT: [[A:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7> +; CHECK-NEXT: store <2 x i8> [[A]], <2 x i8>* [[P:%.*]], align 2 +; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[A]], <i8 1, i8 1> +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %a = ashr <2 x i8> %x, <i8 7, i8 7> + store <2 x i8> %a, <2 x i8>* %p + %r = and <2 x i8> %a, <i8 1, i8 1> + ret <2 x i8> %r +} + +define i32 @ashr_not_lowmask1_use(i32 %x) { +; CHECK-LABEL: @ashr_not_lowmask1_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 254 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 24 + call void @use32(i32 %a) + %r = and i32 %a, 254 + ret i32 %r +} + +define i32 @ashr_not_lowmask2_use(i32 %x) { +; CHECK-LABEL: @ashr_not_lowmask2_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 127 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 24 + call void @use32(i32 %a) + %r = and i32 %a, 127 + ret i32 %r +} + +define i32 @ashr_not_lowmask3_use(i32 %x) { +; CHECK-LABEL: @ashr_not_lowmask3_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 511 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 24 + call void @use32(i32 %a) + %r = and i32 %a, 511 + ret i32 %r } define i32 @test29(i8 %X) { |