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authorTom Stellard <thomas.stellard@amd.com>2016-12-02 02:06:41 +0000
committerTom Stellard <thomas.stellard@amd.com>2016-12-02 02:06:41 +0000
commit06e9e089b83a528a99093167456fdb43ba111309 (patch)
treec68bd9177e3e2373a23cf6030a92f405dd0bc021
parentf782617754f31fddc9112d3a9544e1fd9867f831 (diff)
downloadllvm-06e9e089b83a528a99093167456fdb43ba111309.tar.gz
Revert "Merging r278268:"llvmorg-3.9.1-rc2
This reverts commit r288454. This was committed accidently. llvm-svn: 288456
-rw-r--r--llvm/lib/CodeGen/LiveIntervalAnalysis.cpp5
-rw-r--r--llvm/test/CodeGen/AMDGPU/merge-store-crash.ll36
2 files changed, 0 insertions, 41 deletions
diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
index e2c35b0a1d86..5f3281f6771d 100644
--- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1394,11 +1394,6 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
LaneBitmask LaneMask) {
LiveInterval::iterator LII = LR.find(endIdx);
SlotIndex lastUseIdx;
- if (LII == LR.begin()) {
- // This happens when the function is called for a subregister that only
- // occurs _after_ the range that is to be repaired.
- return;
- }
if (LII != LR.end() && LII->start < endIdx)
lastUseIdx = LII->end;
else
diff --git a/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll b/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
deleted file mode 100644
index ef552e295fd4..000000000000
--- a/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
-
-; This is used to crash in LiveIntervalAnalysis via SILoadStoreOptimizer
-; while fixing up the merge of two ds_write instructions.
-
-@tess_lds = external addrspace(3) global [8192 x i32]
-
-; CHECK-LABEL: {{^}}main:
-; CHECK: ds_write2_b32
-; CHECK: v_mov_b32_e32 v1, v0
-; CHECK: tbuffer_store_format_xyzw v[0:3],
-define amdgpu_vs void @main(i32 inreg %arg) {
-main_body:
- %tmp = load float, float addrspace(3)* undef, align 4
- %tmp1 = load float, float addrspace(3)* undef, align 4
- store float %tmp, float addrspace(3)* null, align 4
- %tmp2 = bitcast float %tmp to i32
- %tmp3 = add nuw nsw i32 0, 1
- %tmp4 = zext i32 %tmp3 to i64
- %tmp5 = getelementptr [8192 x i32], [8192 x i32] addrspace(3)* @tess_lds, i64 0, i64 %tmp4
- %tmp6 = bitcast i32 addrspace(3)* %tmp5 to float addrspace(3)*
- store float %tmp1, float addrspace(3)* %tmp6, align 4
- %tmp7 = bitcast float %tmp1 to i32
- %tmp8 = insertelement <4 x i32> undef, i32 %tmp2, i32 0
- %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp7, i32 1
- %tmp10 = insertelement <4 x i32> %tmp9, i32 undef, i32 2
- %tmp11 = insertelement <4 x i32> %tmp10, i32 undef, i32 3
- call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %tmp11, i32 4, i32 undef, i32 %arg, i32 0, i32 14, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
- ret void
-}
-
-; Function Attrs: nounwind
-declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-attributes #0 = { nounwind }