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| author | Evan Cheng <evan.cheng@apple.com> | 2007-09-11 19:53:28 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-09-11 19:53:28 +0000 |
| commit | 3054dde81377e24f312385c01fcab503d35f2d02 (patch) | |
| tree | faa95280045edc19f0d7a79ebd3c5105a2ecad4d | |
| parent | aeb7d4d7603c5587b1aceb2dd854c7d56b5b9b2a (diff) | |
| download | llvm-3054dde81377e24f312385c01fcab503d35f2d02.tar.gz | |
Added status flags register: EFLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41862 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index c40dcb935500..0d20b59ee01d 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -161,6 +161,9 @@ let Namespace = "X86" in { def ST5 : Register<"ST(5)">, DwarfRegNum<16>; def ST6 : Register<"ST(6)">, DwarfRegNum<17>; def ST7 : Register<"ST(7)">, DwarfRegNum<18>; + + // Status flags register + def EFLAGS : Register<"EFLAGS">; } @@ -516,3 +519,6 @@ def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128, } }]; } + +// Status flags registers. +def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]>; |