summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDaniel Sanders <daniel.sanders@imgtec.com>2015-03-06 12:34:10 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2015-03-06 12:34:10 +0000
commitb362d4b725a06b9a7c2d9a8e99cdb8a01a7d2292 (patch)
tree4e08a481aab66e3a8ea01de5063462bc9da09e4f
parentbcee6089ab0c59ab2c65664696deb2c82c0ce1fe (diff)
downloadllvm-b362d4b725a06b9a7c2d9a8e99cdb8a01a7d2292.tar.gz
Merging r225529:
------------------------------------------------------------------------ r225529 | dsanders | 2015-01-09 17:21:30 +0000 (Fri, 09 Jan 2015) | 18 lines [mips] Add support for accessing $gp as a named register. Summary: Mips Linux uses $gp to hold a pointer to thread info structure and accesses it with a named register. This makes this work for LLVM. The N32 ABI doesn't quite work yet since the frontend generates incorrect IR for this case. It neglects to truncate the 64-bit GPR to a 32-bit value before converting to a pointer. Given correct IR (as in the testcase in this patch), it works correctly. Reviewers: sstankovic, vmedic, atanasyan Reviewed By: atanasyan Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6893 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@231466 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp22
-rw-r--r--lib/Target/Mips/MipsISelLowering.h2
-rw-r--r--test/CodeGen/Mips/named-register-n32.ll18
-rw-r--r--test/CodeGen/Mips/named-register-n64.ll17
-rw-r--r--test/CodeGen/Mips/named-register-o32.ll17
5 files changed, 76 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 8e40668b2fa7..c9ee5fcf8f21 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -3721,3 +3721,25 @@ void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
}
+
+// FIXME? Maybe this could be a TableGen attribute on some registers and
+// this table could be generated automatically from RegInfo.
+unsigned MipsTargetLowering::getRegisterByName(const char* RegName,
+ EVT VT) const {
+ // Named registers is expected to be fairly rare. For now, just support $28
+ // since the linux kernel uses it.
+ if (Subtarget.isGP64bit()) {
+ unsigned Reg = StringSwitch<unsigned>(RegName)
+ .Case("$28", Mips::GP_64)
+ .Default(0);
+ if (Reg)
+ return Reg;
+ } else {
+ unsigned Reg = StringSwitch<unsigned>(RegName)
+ .Case("$28", Mips::GP)
+ .Default(0);
+ if (Reg)
+ return Reg;
+ }
+ report_fatal_error("Invalid register name global variable");
+}
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 23163b73e0a4..b2a97130ecdb 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -262,6 +262,8 @@ namespace llvm {
void HandleByVal(CCState *, unsigned &, unsigned) const override;
+ unsigned getRegisterByName(const char* RegName, EVT VT) const override;
+
protected:
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
diff --git a/test/CodeGen/Mips/named-register-n32.ll b/test/CodeGen/Mips/named-register-n32.ll
new file mode 100644
index 000000000000..e52f8bcb54a6
--- /dev/null
+++ b/test/CodeGen/Mips/named-register-n32.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls,-n64,+n32 < %s | FileCheck %s
+
+define i32* @get_gp() {
+entry:
+ %0 = call i64 @llvm.read_register.i64(metadata !0)
+ %1 = trunc i64 %0 to i32
+ %2 = inttoptr i32 %1 to i32*
+ ret i32* %2
+}
+
+; CHECK-LABEL: get_gp:
+; CHECK: sll $2, $gp, 0
+
+declare i64 @llvm.read_register.i64(metadata)
+
+!llvm.named.register.$28 = !{!0}
+
+!0 = metadata !{metadata !"$28"}
diff --git a/test/CodeGen/Mips/named-register-n64.ll b/test/CodeGen/Mips/named-register-n64.ll
new file mode 100644
index 000000000000..21cd8a9739f4
--- /dev/null
+++ b/test/CodeGen/Mips/named-register-n64.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s
+
+define i32* @get_gp() {
+entry:
+ %0 = call i64 @llvm.read_register.i64(metadata !0)
+ %1 = inttoptr i64 %0 to i32*
+ ret i32* %1
+}
+
+; CHECK-LABEL: get_gp:
+; CHECK: move $2, $gp
+
+declare i64 @llvm.read_register.i64(metadata)
+
+!llvm.named.register.$28 = !{!0}
+
+!0 = metadata !{metadata !"$28"}
diff --git a/test/CodeGen/Mips/named-register-o32.ll b/test/CodeGen/Mips/named-register-o32.ll
new file mode 100644
index 000000000000..033745629505
--- /dev/null
+++ b/test/CodeGen/Mips/named-register-o32.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=mips -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s
+
+define i32* @get_gp() {
+entry:
+ %0 = call i32 @llvm.read_register.i32(metadata !0)
+ %1 = inttoptr i32 %0 to i32*
+ ret i32* %1
+}
+
+; CHECK-LABEL: get_gp:
+; CHECK: move $2, $gp
+
+declare i32 @llvm.read_register.i32(metadata)
+
+!llvm.named.register.$28 = !{!0}
+
+!0 = metadata !{metadata !"$28"}