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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-05-15 10:05:22 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-05-15 10:05:22 +0000 |
| commit | 99d28c459aeaee452e6d0425f9cd9fc33537fa58 (patch) | |
| tree | d4c82c49b09ecc0927fcc19932ea7acea030ec4f | |
| parent | 75cfd0e052ffa4f6841fb7f89d3e3fb9fa1205c8 (diff) | |
| download | llvm-99d28c459aeaee452e6d0425f9cd9fc33537fa58.tar.gz | |
Revert r235869 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
It introduced two regressions (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) on 3 out of 23 cross-compilation
test-runs used by Mips for release validation.
The issue is that on 64-bit targets comparisons such as BEQ compare the whole
GPR64 but incorrectly tell the instruction selector that they operate on
GPR32's. This leads to the elimination of i32->i64 extensions that are actually
required by comparisons to work correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237432 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 8 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/and.ll | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/or.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/xor.ll | 5 |
4 files changed, 13 insertions, 11 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 823f2a016eb0..d6628d408480 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -428,14 +428,6 @@ def : MipsPat<(trunc (assertzext GPR64:$src)), def : MipsPat<(i32 (trunc GPR64:$src)), (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; -// Bypass trunc nodes for bitwise ops. -def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))), - (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>; -def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))), - (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; -def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))), - (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; - // 32-to-64-bit extension def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index eec98831bd63..09d0ef9238af 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -51,7 +51,10 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: and_i32: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $[[T0:[0-9]+]], $4, $5 + ; GP64: sll $2, $[[T0]], 0 %r = and i32 %a, %b ret i32 %r diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll index 910f769ab5ad..21d1d4fca2a3 100644 --- a/test/CodeGen/Mips/llvm-ir/or.ll +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -51,7 +51,11 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: or_i32: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; FIXME: The sll instruction below is redundant. + ; GP64: sll $2, $[[T0]], 0 %r = or i32 %a, %b ret i32 %r diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll index 83107e324320..94dead1eff41 100644 --- a/test/CodeGen/Mips/llvm-ir/xor.ll +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -51,7 +51,10 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: xor_i32: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $[[T0:[0-9]+]], $4, $5 + ; GP64: sll $2, $[[T0]], 0 %r = xor i32 %a, %b ret i32 %r |