diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-04 19:50:17 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-04 19:50:17 +0000 |
| commit | b5344bfff41583c00026e321d6831d4e8790b309 (patch) | |
| tree | 960d04e521b150d77e9bd5c4ca5c7a0beb4cafcb | |
| parent | cb675e58df1e57cb24733282e85e66b09d96a08e (diff) | |
| download | llvm-b5344bfff41583c00026e321d6831d4e8790b309.tar.gz | |
Merging r236307:
------------------------------------------------------------------------
r236307 | thomas.stellard | 2015-04-30 23:44:09 -0400 (Thu, 30 Apr 2015) | 4 lines
R600/SI: Add VCC as an implict def of SI_KILL
When SI_KILL has a register operand, its lowered form writes to vcc.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236452 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 9 | ||||
| -rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.kill.ll | 16 |
2 files changed, 22 insertions, 3 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index ee4bb4c13411..bbedef29303b 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1823,8 +1823,8 @@ def SGPR_USE : InstSI <(outs),(ins), "", []>; // SI pseudo instructions. These are used by the CFG structurizer pass // and should be lowered to ISA instructions prior to codegen. -let mayLoad = 1, mayStore = 1, hasSideEffects = 1, - Uses = [EXEC], Defs = [EXEC] in { +let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { +let Uses = [EXEC], Defs = [EXEC] in { let isBranch = 1, isTerminator = 1 in { @@ -1881,15 +1881,18 @@ def SI_END_CF : InstSI < [(int_SI_end_cf i64:$saved)] >; +} // End Uses = [EXEC], Defs = [EXEC] + +let Uses = [EXEC], Defs = [EXEC,VCC] in { def SI_KILL : InstSI < (outs), (ins VSrc_32:$src), "si_kill $src", [(int_AMDGPU_kill f32:$src)] >; +} // End Uses = [EXEC], Defs = [EXEC,VCC] } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 - // Uses = [EXEC], Defs = [EXEC] let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll b/test/CodeGen/R600/llvm.AMDGPU.kill.ll index d1ff3b1b7d6c..30b0fc2bd73b 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.kill.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll @@ -16,8 +16,24 @@ main_body: ret void } +; SI-LABEL: {{^}}kill_vcc_implicit_def: +; SI-NOT: v_cmp_gt_f32_e32 vcc, +; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}} +; SI: v_cmp_lt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0 +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]] +define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 { +entry: + %tmp0 = fcmp olt float %13, 0.0 + call void @llvm.AMDGPU.kill(float %14) + %tmp1 = select i1 %tmp0, float 1.0, float 0.0 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1) + ret void +} + declare void @llvm.AMDGPU.kill(float) +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="2" } +attributes #1 = { "ShaderType"="0" } !0 = !{!"const", null, i32 1} |