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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-04-28 21:23:04 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-04-28 21:23:04 +0000 |
| commit | efa4fe4455118fdc68ce03c08a36b6e89be5ff90 (patch) | |
| tree | f5db29a9c6dd677456d39609ed06452a3b4dd7cd | |
| parent | fc58d60168988481d45e4792c891d200bc418e7f (diff) | |
| download | llvm-efa4fe4455118fdc68ce03c08a36b6e89be5ff90.tar.gz | |
Merging r232386:
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r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines
R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.
v2: make test more robust
Patch by: Grigori Goronzy
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236040 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/R600/fmax3.f64.ll | 24 |
2 files changed, 25 insertions, 0 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 348431187393..d39cacaf3d66 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -1584,6 +1584,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, case AMDGPUISD::UMAX: case AMDGPUISD::UMIN: { if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG && + N->getValueType(0) != MVT::f64 && getTargetMachine().getOptLevel() > CodeGenOpt::None) return performMin3Max3Combine(N, DCI); break; diff --git a/test/CodeGen/R600/fmax3.f64.ll b/test/CodeGen/R600/fmax3.f64.ll new file mode 100644 index 000000000000..5ca789de2a08 --- /dev/null +++ b/test/CodeGen/R600/fmax3.f64.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare double @llvm.maxnum.f64(double, double) nounwind readnone + +; SI-LABEL: {{^}}test_fmax3_f64: +; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0{{$}} +; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:8 +; SI-DAG: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:16 +; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]] +; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGC]] +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm +define void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind { + %bptr = getelementptr double addrspace(1)* %aptr, i32 1 + %cptr = getelementptr double addrspace(1)* %aptr, i32 2 + %a = load double addrspace(1)* %aptr, align 8 + %b = load double addrspace(1)* %bptr, align 8 + %c = load double addrspace(1)* %cptr, align 8 + %f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone + %f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone + store double %f1, double addrspace(1)* %out, align 8 + ret void +} |