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authorTanya Lattner <tonic@nondot.org>2008-05-12 17:55:39 +0000
committerTanya Lattner <tonic@nondot.org>2008-05-12 17:55:39 +0000
commit3d1d1e1f2902fd479a9bcc392bbdb1e812c84214 (patch)
tree56176b48ed1234925a5233fe58b0229740bf9356
parent3f74e50ff06981aebd410e588330779e275ede35 (diff)
downloadllvm-3d1d1e1f2902fd479a9bcc392bbdb1e812c84214.tar.gz
Merge from mainline.
When transforming a vector_shuffle to a load, the base address must not be an undef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@50981 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp2
-rw-r--r--test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll10
2 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index d2d76671e949..307aeae1b22c 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -6283,6 +6283,8 @@ static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
return false;
if (!Base) {
Base = Elt.Val;
+ if (Base->getOpcode() == ISD::UNDEF)
+ return false;
continue;
}
if (Elt.getOpcode() == ISD::UNDEF)
diff --git a/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
new file mode 100644
index 000000000000..9bcd1f374dd6
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+
+define fastcc void @glgVectorFloatConversion() nounwind {
+ %tmp12745 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=1]
+ %tmp12773 = insertelement <4 x float> %tmp12745, float 1.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp12774 = insertelement <4 x float> %tmp12773, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp12775 = insertelement <4 x float> %tmp12774, float 1.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp12775, <4 x float>* null, align 16
+ unreachable
+}