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| author | luxufan <932494295@qq.com> | 2022-01-04 19:39:07 +0800 |
|---|---|---|
| committer | luxufan <932494295@qq.com> | 2022-01-04 20:05:50 +0800 |
| commit | 95b74d4db0686a8d55fdae1af4e985ea52b2c572 (patch) | |
| tree | f9b44ce9bba67abd7b22085f75002f23b3b3939c | |
| parent | 1c66691ea770c2049bbc5a27fa6e998e01a7eaf8 (diff) | |
| download | llvm-95b74d4db0686a8d55fdae1af4e985ea52b2c572.tar.gz | |
[JITLink] Improve extractBits function
Address the advice proposed at patch D105429 . Use [Low, Low+size) to represent bits.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D107250
| -rw-r--r-- | llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp index b057788ce3ef..26ec79ea50cf 100644 --- a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp @@ -157,8 +157,8 @@ static Expected<const Edge &> getRISCVPCRelHi20(const Edge &E) { "No HI20 PCREL relocation type be found for LO12 PCREL relocation type"); } -static uint32_t extractBits(uint64_t Num, unsigned High, unsigned Low) { - return (Num & ((1ULL << (High + 1)) - 1)) >> Low; +static uint32_t extractBits(uint32_t Num, unsigned Low, unsigned Size) { + return (Num & (((1ULL << (Size + 1)) - 1) << Low)) >> Low; } class ELFJITLinker_riscv : public JITLinker<ELFJITLinker_riscv> { @@ -238,8 +238,8 @@ private: int64_t Value = RelHI20->getTarget().getAddress() + RelHI20->getAddend() - E.getTarget().getAddress(); int64_t Lo = Value & 0xFFF; - uint32_t Imm31_25 = extractBits(Lo, 11, 5) << 25; - uint32_t Imm11_7 = extractBits(Lo, 4, 0) << 7; + uint32_t Imm31_25 = extractBits(Lo, 5, 7) << 25; + uint32_t Imm11_7 = extractBits(Lo, 0, 5) << 7; uint32_t RawInstr = *(little32_t *)FixupPtr; *(little32_t *)FixupPtr = (RawInstr & 0x1FFF07F) | Imm31_25 | Imm11_7; |