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| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2002-09-05 18:36:41 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2002-09-05 18:36:41 +0000 |
| commit | 68f716190baa08675793adba428605797eb658a4 (patch) | |
| tree | c3fe28ad336544641307288108b86064e0127562 /include/llvm | |
| parent | f36f06bb6097e1bf64211566483dce51eb2061d6 (diff) | |
| download | llvm-68f716190baa08675793adba428605797eb658a4.tar.gz | |
Add new function MachineInstrInfo::CreateZeroExtensionInstructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3582 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
| -rw-r--r-- | include/llvm/Target/MachineInstrInfo.h | 20 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 20 |
2 files changed, 36 insertions, 4 deletions
diff --git a/include/llvm/Target/MachineInstrInfo.h b/include/llvm/Target/MachineInstrInfo.h index 6a0ff0a85eab..855840caf7f8 100644 --- a/include/llvm/Target/MachineInstrInfo.h +++ b/include/llvm/Target/MachineInstrInfo.h @@ -299,15 +299,31 @@ public: // Create instruction sequence to produce a sign-extended register value // from an arbitrary sized value (sized in bits, not bytes). + // The generated instructions are appended to `mvec'. + // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // virtual void CreateSignExtensionInstructions(const TargetMachine& target, Function* F, - Value* unsignedSrcVal, + Value* srcVal, unsigned int srcSizeInBits, Value* dest, std::vector<MachineInstr*>& mvec, - MachineCodeForInstruction& mcfi)const=0; + MachineCodeForInstruction& mcfi) const=0; + + // Create instruction sequence to produce a zero-extended register value + // from an arbitrary sized value (sized in bits, not bytes). + // The generated instructions are appended to `mvec'. + // Any temp. registers (TmpInstruction) created are recorded in mcfi. + // Any stack space required is allocated via mcff. + // + virtual void CreateZeroExtensionInstructions(const TargetMachine& target, + Function* F, + Value* srcVal, + unsigned int srcSizeInBits, + Value* dest, + std::vector<MachineInstr*>& mvec, + MachineCodeForInstruction& mcfi) const=0; }; #endif diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 6a0ff0a85eab..855840caf7f8 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -299,15 +299,31 @@ public: // Create instruction sequence to produce a sign-extended register value // from an arbitrary sized value (sized in bits, not bytes). + // The generated instructions are appended to `mvec'. + // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // virtual void CreateSignExtensionInstructions(const TargetMachine& target, Function* F, - Value* unsignedSrcVal, + Value* srcVal, unsigned int srcSizeInBits, Value* dest, std::vector<MachineInstr*>& mvec, - MachineCodeForInstruction& mcfi)const=0; + MachineCodeForInstruction& mcfi) const=0; + + // Create instruction sequence to produce a zero-extended register value + // from an arbitrary sized value (sized in bits, not bytes). + // The generated instructions are appended to `mvec'. + // Any temp. registers (TmpInstruction) created are recorded in mcfi. + // Any stack space required is allocated via mcff. + // + virtual void CreateZeroExtensionInstructions(const TargetMachine& target, + Function* F, + Value* srcVal, + unsigned int srcSizeInBits, + Value* dest, + std::vector<MachineInstr*>& mvec, + MachineCodeForInstruction& mcfi) const=0; }; #endif |