summaryrefslogtreecommitdiff
path: root/lib/CodeGen/LiveIntervalUnion.cpp
diff options
context:
space:
mode:
authorAndrew Trick <atrick@apple.com>2010-12-09 18:15:21 +0000
committerAndrew Trick <atrick@apple.com>2010-12-09 18:15:21 +0000
commitb853e6c3702149cdbbd6fa404334e3ba0055641a (patch)
tree2daa08a7cd8703e8d397588a903545c4dfb965d9 /lib/CodeGen/LiveIntervalUnion.cpp
parentf2f516fc2680168caac9981a4dd17cc37c639c71 (diff)
downloadllvm-b853e6c3702149cdbbd6fa404334e3ba0055641a.tar.gz
Added register reassignment prototype to RAGreedy. It's a simple
heuristic to reshuffle register assignments when we can't find an available reg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121388 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LiveIntervalUnion.cpp')
-rw-r--r--lib/CodeGen/LiveIntervalUnion.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/CodeGen/LiveIntervalUnion.cpp b/lib/CodeGen/LiveIntervalUnion.cpp
index 1fca034fdcb3..d5c7bf08eb65 100644
--- a/lib/CodeGen/LiveIntervalUnion.cpp
+++ b/lib/CodeGen/LiveIntervalUnion.cpp
@@ -247,10 +247,13 @@ collectInterferingVRegs(unsigned MaxInterferingRegs) {
if (!IR.LiveUnionI.value()->isSpillable())
SeenUnspillableVReg = true;
- InterferingVRegs.push_back(IR.LiveUnionI.value());
if (InterferingVRegs.size() == MaxInterferingRegs)
+ // Leave SeenAllInterferences set to false to indicate that at least one
+ // interference exists beyond those we collected.
return MaxInterferingRegs;
+ InterferingVRegs.push_back(IR.LiveUnionI.value());
+
// Cache the most recent interfering vreg to bypass isSeenInterference.
RecentInterferingVReg = IR.LiveUnionI.value();
++IR.LiveUnionI;