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| author | Simon Dardis <simon.dardis@imgtec.com> | 2017-10-16 14:20:22 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2017-10-16 14:20:22 +0000 |
| commit | 05cc2c7d76c3ffa504a6096aeedf0a1996d3d4f1 (patch) | |
| tree | bd08f97a5490d1933d2d949eaef1709474bdbb2f /lib/Target/Mips/MCTargetDesc | |
| parent | b5d9fa1867a288fca27563c4a07c900e7db6fac6 (diff) | |
| download | llvm-05cc2c7d76c3ffa504a6096aeedf0a1996d3d4f1.tar.gz | |
[mips][micromips] Fix (dis)assembly of bc1(t|f)
Previously these instructions were marked codegen only and had
an under-specified instruction description that did not record the
fcc register.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D38847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315905 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MCTargetDesc')
0 files changed, 0 insertions, 0 deletions