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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-19 20:21:18 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-19 20:21:18 +0000 |
| commit | f06cb2b207c9a4a99e9d8f2b45f9b48dfddc15ee (patch) | |
| tree | e06dc2c502d92b4a53f33c2a7c2a75286a68f215 /test/CodeGen/Mips/fcopysign.ll | |
| parent | 1e2ec6abd4e150ac87d6cde3133fa9895f63c74c (diff) | |
| download | llvm-f06cb2b207c9a4a99e9d8f2b45f9b48dfddc15ee.tar.gz | |
Add patterns for matching immediates whose lower 16-bit is cleared. These
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/fcopysign.ll')
| -rw-r--r-- | test/CodeGen/Mips/fcopysign.ll | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index 950c437072a5..e494fe2291e3 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -5,9 +5,8 @@ define double @func0(double %d0, double %d1) nounwind readnone { entry: ; MIPS32-EL: func0: -; MIPS32-EL: lui $[[T1:[0-9]+]], 32768 -; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 ; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15 +; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768 ; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]] ; MIPS32-EL: lui $[[T0:[0-9]+]], 32767 ; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 @@ -18,9 +17,8 @@ entry: ; MIPS32-EL: mtc1 $[[LO0]], $f0 ; MIPS32-EL: mtc1 $[[OR]], $f1 ; -; MIPS32-EB: lui $[[T1:[0-9]+]], 32768 -; MIPS32-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0 ; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14 +; MIPS32-EB: lui $[[MSK1:[0-9]+]], 32768 ; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] ; MIPS32-EB: lui $[[T0:[0-9]+]], 32767 ; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 @@ -46,9 +44,8 @@ declare double @copysign(double, double) nounwind readnone define float @func1(float %f0, float %f1) nounwind readnone { entry: ; MIPS32-EL: func1: -; MIPS32-EL: lui $[[T1:[0-9]+]], 32768 -; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 ; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14 +; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768 ; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]] ; MIPS32-EL: lui $[[T0:[0-9]+]], 32767 ; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 |