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authorMatthias Braun <matze@braunis.de>2016-03-01 20:03:11 +0000
committerMatthias Braun <matze@braunis.de>2016-03-01 20:03:11 +0000
commit279476d30d534aaccaec90288e723a8ab7ab1680 (patch)
treee00e265129f481483b5dea3446fc5b9120c2beec /utils
parent47e3ade685cbc66c55bcf58923ef37ef4b5b49f7 (diff)
downloadllvm-279476d30d534aaccaec90288e723a8ab7ab1680.tar.gz
TableGen: Add hasNoSchedulingInfo to instructions
This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information. This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs. Differential Revision: http://reviews.llvm.org/D17728 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262383 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/CodeGenInstruction.cpp1
-rw-r--r--utils/TableGen/CodeGenInstruction.h1
-rw-r--r--utils/TableGen/CodeGenSchedule.cpp3
3 files changed, 4 insertions, 1 deletions
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index bd26beb35677..ec802363030e 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -324,6 +324,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isExtractSubreg = R->getValueAsBit("isExtractSubreg");
isInsertSubreg = R->getValueAsBit("isInsertSubreg");
isConvergent = R->getValueAsBit("isConvergent");
+ hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
bool Unset;
mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 8f01abd5403c..bfdc2c62dce1 100644
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -257,6 +257,7 @@ namespace llvm {
bool isExtractSubreg : 1;
bool isInsertSubreg : 1;
bool isConvergent : 1;
+ bool hasNoSchedulingInfo : 1;
std::string DeprecatedReason;
bool HasComplexDeprecationPredicate;
diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index ecae859c9dd1..0bce99636bc9 100644
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -527,7 +527,8 @@ void CodeGenSchedModels::collectSchedClasses() {
std::string InstName = Inst->TheDef->getName();
unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
if (!SCIdx) {
- dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
+ if (!Inst->hasNoSchedulingInfo)
+ dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
continue;
}
CodeGenSchedClass &SC = getSchedClass(SCIdx);